From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefano Babic Date: Mon, 29 Sep 2014 10:27:08 +0200 Subject: [U-Boot] [PATCH v3 3/5] imx: mx6dlarm2: Add support for i.MX6DL arm2 DDR3 board In-Reply-To: <542914EF.8030708@denx.de> References: <1410229021-2995-1-git-send-email-B37916@freescale.com> <1410229021-2995-3-git-send-email-B37916@freescale.com> <542914EF.8030708@denx.de> Message-ID: <542917DC.1090407@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 29/09/2014 10:14, Stefano Babic wrote: > On 09/09/2014 04:16, Ye.Li wrote: >> This patch adds the i.MX6DL arm2 board support. The i.MX6DL ARM2 >> shared the same board with i.MX6Q ARM2 board since the i.MX6DL is >> pin-pin compatible with i.MX6Q. >> >> The patch also support the DDR 32-BIT mode option. Please define >> CONFIG_DDR_32BIT in the board configure file to enable DDR 32-BIT >> mode.But due to the board design, it's 64bit DDR buswidth physically, >> so, if you CONFIG_DDR_32BIT, the DDR memory size will be half of it. >> >> Signed-off-by: Ye.Li >> --- > > Applied to u-boot-imx, thanks ! Not really. You have not added your name as maintainer and there are still some warnings: WARNING: no status info for 'mx6qarm2_lpddr2' WARNING: no maintainers for 'mx6qarm2_lpddr2' WARNING: no status info for 'mx6dlarm2' WARNING: no maintainers for 'mx6dlarm2' WARNING: no status info for 'mx6dlarm2_lpddr2' WARNING: no maintainers for 'mx6dlarm2_lpddr2' Please add your status and your name as Maintainer to the new board. I have applied in the series patches 1,2, and 4, letting out 3 and 5 that must be fixed. Please fix and repost, thanks ! Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de =====================================================================