From mboxrd@z Thu Jan 1 00:00:00 1970 From: York Sun Date: Wed, 1 Oct 2014 20:29:10 -0700 Subject: [U-Boot] Commit 294b91a5817147d4b7f47be2ac69bac2a1f26491 broke mpc85xx In-Reply-To: <1412216135.13320.388.camel@snotra.buserror.net> References: <542C2B84.1090706@freescale.com> <1412216135.13320.388.camel@snotra.buserror.net> Message-ID: <542CC686.9090208@freescale.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 10/01/2014 07:15 PM, Scott Wood wrote: >> >> I can change init sequence as far as I put initr_unlock_ram_in_cache before >> initr_malloc, T4240QDS still boots. > > Yes, we shouldn't have any reason to keep the cache locked that long. > >> I examine the code but don't understand why I have to do so. P4080DS doesn't >> suffer this issue. I am going to seek some help from Scott and other in-house >> experts. > > My guess is that it has to do with the way caches work on e6500. We try > to lock lines in L1, but L1 can't hold dirty lines, so perhaps the hang > comes when the DDR activity evicts the dirty lines from L2 (where they > weren't locked). > Scott, Thanks for looking into this. I can propose a fix, but first I will have to do a thorough test on all varieties of 85xx board we have. York