[U-Boot] [PATCH] nitrogen6x: Update DDR timings for 2G memory arrangement

[U-Boot] [PATCH] nitrogen6x: Update DDR timings for 2G memory arrangement

[Eric Nelson]

Update DDR calibration settings based on a larger test set.

The initial values were gathered on a small number of boards,
and have been found to fail on some boards under load.

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
---
 board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg b/board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg
index bb5716e..1096f77 100644
--- a/board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg
+++ b/board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg
@@ -24,18 +24,18 @@ DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
 DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
 DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
 DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
-DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43040319
-DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x03040279
-DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43040321
-DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03030251
-DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4d434248
-DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x42413c4d
-DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x34424543
-DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x49324933
-DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001a0017
-DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
-DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00170027
-DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x000a001f
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42740304
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x026e0265
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x02750306
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02720244
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x463d4041
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x42413c47
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x37414441
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4633473b
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0025001f
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x00290027
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001f002b
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x000f0029
 DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
 DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
 DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
-- 
1.9.1

[U-Boot] [PATCH] nitrogen6x: Update DDR timings for 2G memory arrangement

[Stefano Babic]

On 02/10/2014 03:33, Eric Nelson wrote:
> Update DDR calibration settings based on a larger test set.
> 
> The initial values were gathered on a small number of boards,
> and have been found to fail on some boards under load.
> 
> Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
> ---



Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic



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