* [U-Boot] [U-boot] [Patch v4 1/6] ARM: keystone2: add K2L device hardware definitions
2014-10-14 23:55 [U-Boot] [U-boot] [Patch v4 0/6] keystone2: add k2l SoC and k2l_evm board support Ivan Khoronzhuk
@ 2014-10-14 23:55 ` Ivan Khoronzhuk
2014-10-14 23:55 ` [U-Boot] [U-boot] [Patch v4 2/6] keystone2: clock: add K2L clock definitions and commands Ivan Khoronzhuk
` (4 subsequent siblings)
5 siblings, 0 replies; 13+ messages in thread
From: Ivan Khoronzhuk @ 2014-10-14 23:55 UTC (permalink / raw)
To: u-boot
From: Hao Zhang <hzhang@ti.com>
This patch adds hardware definitions specific to Keystone II
Lamar (K2L) SoC.
Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
---
arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 2 -
arch/arm/include/asm/arch-keystone/hardware-k2l.h | 74 ++++++++++++++++++++++
arch/arm/include/asm/arch-keystone/hardware.h | 13 ++++
3 files changed, 87 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/include/asm/arch-keystone/hardware-k2l.h
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
index 43c2c42..2db806c 100644
--- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
@@ -10,8 +10,6 @@
#ifndef __ASM_ARCH_HARDWARE_K2HK_H
#define __ASM_ARCH_HARDWARE_K2HK_H
-#define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
-
#define KS2_ARM_PLL_EN BIT(13)
/* PA SS Registers */
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2l.h b/arch/arm/include/asm/arch-keystone/hardware-k2l.h
new file mode 100644
index 0000000..3402d0c
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2l.h
@@ -0,0 +1,74 @@
+/*
+ * K2L: SoC definitions
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_K2L_H
+#define __ASM_ARCH_HARDWARE_K2L_H
+
+#define KS2_ARM_PLL_EN BIT(13)
+
+/* PA SS Registers */
+#define KS2_PASS_BASE 0x26000000
+
+/* Power and Sleep Controller (PSC) Domains */
+#define KS2_LPSC_MOD 0
+#define KS2_LPSC_DFE_IQN_SYS 1
+#define KS2_LPSC_USB 2
+#define KS2_LPSC_EMIF25_SPI 3
+#define KS2_LPSC_TSIP 4
+#define KS2_LPSC_DEBUGSS_TRC 5
+#define KS2_LPSC_TETB_TRC 6
+#define KS2_LPSC_PKTPROC 7
+#define KS2_LPSC_PA KS2_LPSC_PKTPROC
+#define KS2_LPSC_SGMII 8
+#define KS2_LPSC_CPGMAC KS2_LPSC_SGMII
+#define KS2_LPSC_CRYPTO 9
+#define KS2_LPSC_PCIE0 10
+#define KS2_LPSC_PCIE1 11
+#define KS2_LPSC_JESD_MISC 12
+#define KS2_LPSC_CHIP_SRSS 13
+#define KS2_LPSC_MSMC 14
+#define KS2_LPSC_GEM_1 16
+#define KS2_LPSC_GEM_2 17
+#define KS2_LPSC_GEM_3 18
+#define KS2_LPSC_EMIF4F_DDR3 23
+#define KS2_LPSC_TAC 25
+#define KS2_LPSC_RAC 26
+#define KS2_LPSC_DDUC4X_CFR2X_BB 27
+#define KS2_LPSC_FFTC_A 28
+#define KS2_LPSC_OSR 34
+#define KS2_LPSC_TCP3D_0 35
+#define KS2_LPSC_TCP3D_1 37
+#define KS2_LPSC_VCP2X4_A 39
+#define KS2_LPSC_VCP2X4_B 40
+#define KS2_LPSC_VCP2X4_C 41
+#define KS2_LPSC_VCP2X4_D 42
+#define KS2_LPSC_BCP 47
+#define KS2_LPSC_DPD4X 48
+#define KS2_LPSC_FFTC_B 49
+#define KS2_LPSC_IQN_AIL 50
+
+/* Chip Interrupt Controller */
+#define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3
+#define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D
+
+/* Number of DSP cores */
+#define KS2_NUM_DSPS 4
+
+/* NETCP pktdma */
+#define KS2_NETCP_PDMA_CTRL_BASE 0x26186000
+#define KS2_NETCP_PDMA_TX_BASE 0x26187000
+#define KS2_NETCP_PDMA_TX_CH_NUM 21
+#define KS2_NETCP_PDMA_RX_BASE 0x26188000
+#define KS2_NETCP_PDMA_RX_CH_NUM 91
+#define KS2_NETCP_PDMA_SCHED_BASE 0x26186100
+#define KS2_NETCP_PDMA_RX_FLOW_BASE 0x26189000
+#define KS2_NETCP_PDMA_RX_FLOW_NUM 96
+#define KS2_NETCP_PDMA_TX_SND_QUEUE 896
+
+#endif /* __ASM_ARCH_HARDWARE_K2L_H */
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h
index c1642a5..adae69e 100644
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -143,6 +143,7 @@ typedef volatile unsigned int *dv_reg_p;
/* Device speed */
#define KS2_REV1_DEVSPEED (KS2_DEVICE_STATE_CTRL_BASE + 0xc98)
#define KS2_EFUSE_BOOTROM (KS2_DEVICE_STATE_CTRL_BASE + 0xc90)
+#define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
/* Queue manager */
#define KS2_QM_BASE_ADDRESS 0x23a80000
@@ -177,6 +178,10 @@ typedef volatile unsigned int *dv_reg_p;
#include <asm/arch/hardware-k2e.h>
#endif
+#ifdef CONFIG_SOC_K2L
+#include <asm/arch/hardware-k2l.h>
+#endif
+
#ifndef __ASSEMBLY__
static inline int cpu_is_k2hk(void)
{
@@ -194,6 +199,14 @@ static inline int cpu_is_k2e(void)
return (part_no == 0xb9a6) ? 1 : 0;
}
+static inline int cpu_is_k2l(void)
+{
+ unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG);
+ unsigned int part_no = (jtag_id >> 12) & 0xffff;
+
+ return (part_no == 0xb9a7) ? 1 : 0;
+}
+
static inline int cpu_revision(void)
{
unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG);
--
1.8.3.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* [U-Boot] [U-boot] [Patch v4 2/6] keystone2: clock: add K2L clock definitions and commands
2014-10-14 23:55 [U-Boot] [U-boot] [Patch v4 0/6] keystone2: add k2l SoC and k2l_evm board support Ivan Khoronzhuk
2014-10-14 23:55 ` [U-Boot] [U-boot] [Patch v4 1/6] ARM: keystone2: add K2L device hardware definitions Ivan Khoronzhuk
@ 2014-10-14 23:55 ` Ivan Khoronzhuk
2014-10-20 15:13 ` Tom Rini
2014-10-14 23:55 ` [U-Boot] [U-boot] [Patch v4 3/6] keystone2: msmc: add MSMC cache coherency support for K2L SOC Ivan Khoronzhuk
` (3 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Ivan Khoronzhuk @ 2014-10-14 23:55 UTC (permalink / raw)
To: u-boot
From: Hao Zhang <hzhang@ti.com>
This patch adds clock definitions and commands to support Keystone II
K2L SOC.
Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
---
arch/arm/cpu/armv7/keystone/Makefile | 1 +
arch/arm/cpu/armv7/keystone/clock-k2l.c | 138 +++++++++++++++++++++++++
arch/arm/cpu/armv7/keystone/cmd_clock.c | 10 ++
arch/arm/include/asm/arch-keystone/clock-k2l.h | 88 ++++++++++++++++
arch/arm/include/asm/arch-keystone/clock.h | 4 +
5 files changed, 241 insertions(+)
create mode 100644 arch/arm/cpu/armv7/keystone/clock-k2l.c
create mode 100644 arch/arm/include/asm/arch-keystone/clock-k2l.h
diff --git a/arch/arm/cpu/armv7/keystone/Makefile b/arch/arm/cpu/armv7/keystone/Makefile
index 3d8fb70..4750371 100644
--- a/arch/arm/cpu/armv7/keystone/Makefile
+++ b/arch/arm/cpu/armv7/keystone/Makefile
@@ -10,6 +10,7 @@ obj-y += psc.o
obj-y += clock.o
obj-$(CONFIG_SOC_K2HK) += clock-k2hk.o
obj-$(CONFIG_SOC_K2E) += clock-k2e.o
+obj-$(CONFIG_SOC_K2L) += clock-k2l.o
obj-y += cmd_clock.o
obj-y += cmd_mon.o
obj-y += msmc.o
diff --git a/arch/arm/cpu/armv7/keystone/clock-k2l.c b/arch/arm/cpu/armv7/keystone/clock-k2l.c
new file mode 100644
index 0000000..1c5e4d5
--- /dev/null
+++ b/arch/arm/cpu/armv7/keystone/clock-k2l.c
@@ -0,0 +1,138 @@
+/*
+ * Keystone2: get clk rate for K2L
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clock_defs.h>
+
+const struct keystone_pll_regs keystone_pll_regs[] = {
+ [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
+ [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
+ [TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
+ [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
+};
+
+int dev_speeds[] = {
+ SPD800,
+ SPD1000,
+ SPD1200,
+ SPD800,
+ SPD800,
+ SPD800,
+ SPD800,
+ SPD800,
+ SPD1200,
+ SPD1000,
+ SPD800,
+ SPD800,
+ SPD800,
+};
+
+int arm_speeds[] = {
+ SPD800,
+ SPD1000,
+ SPD1200,
+ SPD1350,
+ SPD1400,
+ SPD800,
+ SPD1400,
+ SPD1350,
+ SPD1200,
+ SPD1000,
+ SPD800,
+ SPD800,
+ SPD800,
+};
+
+/**
+ * pll_freq_get - get pll frequency
+ * Fout = Fref * NF(mult) / NR(prediv) / OD
+ * @pll: pll identifier
+ */
+static unsigned long pll_freq_get(int pll)
+{
+ unsigned long mult = 1, prediv = 1, output_div = 2;
+ unsigned long ret;
+ u32 tmp, reg;
+
+ if (pll == CORE_PLL) {
+ ret = external_clk[sys_clk];
+ if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
+ /* PLL mode */
+ tmp = __raw_readl(KS2_MAINPLLCTL0);
+ prediv = (tmp & PLL_DIV_MASK) + 1;
+ mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
+ (pllctl_reg_read(pll, mult) &
+ PLLM_MULT_LO_MASK)) + 1;
+ output_div = ((pllctl_reg_read(pll, secctl) >>
+ PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
+
+ ret = ret / prediv / output_div * mult;
+ }
+ } else {
+ switch (pll) {
+ case PASS_PLL:
+ ret = external_clk[pa_clk];
+ reg = KS2_PASSPLLCTL0;
+ break;
+ case TETRIS_PLL:
+ ret = external_clk[tetris_clk];
+ reg = KS2_ARMPLLCTL0;
+ break;
+ case DDR3_PLL:
+ ret = external_clk[ddr3_clk];
+ reg = KS2_DDR3APLLCTL0;
+ break;
+ default:
+ return 0;
+ }
+
+ tmp = __raw_readl(reg);
+ if (!(tmp & PLLCTL_BYPASS)) {
+ /* Bypass disabled */
+ prediv = (tmp & PLL_DIV_MASK) + 1;
+ mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
+ output_div = ((tmp >> PLL_CLKOD_SHIFT) &
+ PLL_CLKOD_MASK) + 1;
+ ret = ((ret / prediv) * mult) / output_div;
+ }
+ }
+
+ return ret;
+}
+
+unsigned long clk_get_rate(unsigned int clk)
+{
+ switch (clk) {
+ case core_pll_clk: return pll_freq_get(CORE_PLL);
+ case pass_pll_clk: return pll_freq_get(PASS_PLL);
+ case tetris_pll_clk: return pll_freq_get(TETRIS_PLL);
+ case ddr3_pll_clk: return pll_freq_get(DDR3_PLL);
+ case sys_clk0_1_clk:
+ case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1);
+ case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2);
+ case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3);
+ case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4);
+ case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2;
+ case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3;
+ case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4;
+ case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6;
+ case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8;
+ case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12;
+ case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24;
+ case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3;
+ case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4;
+ case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6;
+ case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12;
+ default:
+ break;
+ }
+
+ return 0;
+}
diff --git a/arch/arm/cpu/armv7/keystone/cmd_clock.c b/arch/arm/cpu/armv7/keystone/cmd_clock.c
index d97c95b..9204887 100644
--- a/arch/arm/cpu/armv7/keystone/cmd_clock.c
+++ b/arch/arm/cpu/armv7/keystone/cmd_clock.c
@@ -72,6 +72,13 @@ U_BOOT_CMD(
"<pa|ddr3> <mult> <div> <OD>\n"
);
#endif
+#ifdef CONFIG_SOC_K2L
+U_BOOT_CMD(
+ pllset, 5, 0, do_pll_cmd,
+ "set pll multiplier and pre divider",
+ "<pa|arm|ddr3> <mult> <div> <OD>\n"
+);
+#endif
int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
@@ -101,6 +108,9 @@ U_BOOT_CMD(
#ifdef CONFIG_SOC_K2E
"See the 'enum clk_e' in the clock-k2e.h for clk indexes\n"
#endif
+#ifdef CONFIG_SOC_K2L
+ "See the 'enum clk_e' in the clock-k2l.h for clk indexes\n"
+#endif
);
int do_psc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
diff --git a/arch/arm/include/asm/arch-keystone/clock-k2l.h b/arch/arm/include/asm/arch-keystone/clock-k2l.h
new file mode 100644
index 0000000..8cacee0
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/clock-k2l.h
@@ -0,0 +1,88 @@
+/*
+ * K2L: Clock management APIs
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_CLOCK_K2L_H
+#define __ASM_ARCH_CLOCK_K2L_H
+
+enum ext_clk_e {
+ sys_clk,
+ alt_core_clk,
+ pa_clk,
+ tetris_clk,
+ ddr3_clk,
+ pcie_clk,
+ sgmii_clk,
+ usb_clk,
+ rp1_clk,
+ ext_clk_count /* number of external clocks */
+};
+
+extern unsigned int external_clk[ext_clk_count];
+
+enum clk_e {
+ core_pll_clk,
+ pass_pll_clk,
+ tetris_pll_clk,
+ ddr3_pll_clk,
+ sys_clk0_clk,
+ sys_clk0_1_clk,
+ sys_clk0_2_clk,
+ sys_clk0_3_clk,
+ sys_clk0_4_clk,
+ sys_clk0_6_clk,
+ sys_clk0_8_clk,
+ sys_clk0_12_clk,
+ sys_clk0_24_clk,
+ sys_clk1_clk,
+ sys_clk1_3_clk,
+ sys_clk1_4_clk,
+ sys_clk1_6_clk,
+ sys_clk1_12_clk,
+ sys_clk2_clk,
+ sys_clk3_clk
+};
+
+#define KS2_CLK1_6 sys_clk0_6_clk
+
+/* PLL identifiers */
+enum pll_type_e {
+ CORE_PLL,
+ PASS_PLL,
+ TETRIS_PLL,
+ DDR3_PLL,
+};
+
+enum {
+ SPD800,
+ SPD1000,
+ SPD1200,
+ SPD1350,
+ SPD1400,
+ SPD_RSV
+};
+
+#define CORE_PLL_799 {CORE_PLL, 13, 1, 2}
+#define CORE_PLL_983 {CORE_PLL, 16, 1, 2}
+#define CORE_PLL_1167 {CORE_PLL, 19, 1, 2}
+#define CORE_PLL_1228 {CORE_PLL, 20, 1, 2}
+#define PASS_PLL_1228 {PASS_PLL, 20, 1, 2}
+#define PASS_PLL_983 {PASS_PLL, 16, 1, 2}
+#define PASS_PLL_1050 {PASS_PLL, 205, 12, 2}
+#define TETRIS_PLL_491 {TETRIS_PLL, 8, 1, 2}
+#define TETRIS_PLL_737 {TETRIS_PLL, 12, 1, 2}
+#define TETRIS_PLL_799 {TETRIS_PLL, 13, 1, 2}
+#define TETRIS_PLL_983 {TETRIS_PLL, 16, 1, 2}
+#define TETRIS_PLL_1167 {TETRIS_PLL, 19, 1, 2}
+#define TETRIS_PLL_1228 {TETRIS_PLL, 20, 1, 2}
+#define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2}
+#define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4}
+#define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2}
+#define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6}
+
+#endif
diff --git a/arch/arm/include/asm/arch-keystone/clock.h b/arch/arm/include/asm/arch-keystone/clock.h
index dae000e..bc31267 100644
--- a/arch/arm/include/asm/arch-keystone/clock.h
+++ b/arch/arm/include/asm/arch-keystone/clock.h
@@ -20,6 +20,10 @@
#include <asm/arch/clock-k2e.h>
#endif
+#ifdef CONFIG_SOC_K2L
+#include <asm/arch/clock-k2l.h>
+#endif
+
#define MAIN_PLL CORE_PLL
#include <asm/types.h>
--
1.8.3.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* [U-Boot] [U-boot] [Patch v4 2/6] keystone2: clock: add K2L clock definitions and commands
2014-10-14 23:55 ` [U-Boot] [U-boot] [Patch v4 2/6] keystone2: clock: add K2L clock definitions and commands Ivan Khoronzhuk
@ 2014-10-20 15:13 ` Tom Rini
2014-10-20 15:41 ` Ivan Khoronzhuk
0 siblings, 1 reply; 13+ messages in thread
From: Tom Rini @ 2014-10-20 15:13 UTC (permalink / raw)
To: u-boot
On Wed, Oct 15, 2014 at 02:55:28AM +0300, Ivan Khoronzhuk wrote:
> From: Hao Zhang <hzhang@ti.com>
>
> This patch adds clock definitions and commands to support Keystone II
> K2L SOC.
>
> Acked-by: Vitaly Andrianov <vitalya@ti.com>
> Signed-off-by: Hao Zhang <hzhang@ti.com>
> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
[snip]
> diff --git a/arch/arm/cpu/armv7/keystone/cmd_clock.c b/arch/arm/cpu/armv7/keystone/cmd_clock.c
> index d97c95b..9204887 100644
> --- a/arch/arm/cpu/armv7/keystone/cmd_clock.c
> +++ b/arch/arm/cpu/armv7/keystone/cmd_clock.c
> @@ -72,6 +72,13 @@ U_BOOT_CMD(
> "<pa|ddr3> <mult> <div> <OD>\n"
> );
> #endif
> +#ifdef CONFIG_SOC_K2L
> +U_BOOT_CMD(
> + pllset, 5, 0, do_pll_cmd,
> + "set pll multiplier and pre divider",
> + "<pa|arm|ddr3> <mult> <div> <OD>\n"
> +);
> +#endif
>
> int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> {
> @@ -101,6 +108,9 @@ U_BOOT_CMD(
> #ifdef CONFIG_SOC_K2E
> "See the 'enum clk_e' in the clock-k2e.h for clk indexes\n"
> #endif
> +#ifdef CONFIG_SOC_K2L
> + "See the 'enum clk_e' in the clock-k2l.h for clk indexes\n"
> +#endif
> );
I'm not going to block on all of this duplication, but we need to think
how to do this cleaner so that the next K2 variant doesn't expand this
mess further. Thanks!
--
Tom
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^ permalink raw reply [flat|nested] 13+ messages in thread* [U-Boot] [U-boot] [Patch v4 2/6] keystone2: clock: add K2L clock definitions and commands
2014-10-20 15:13 ` Tom Rini
@ 2014-10-20 15:41 ` Ivan Khoronzhuk
2014-10-20 15:55 ` Tom Rini
0 siblings, 1 reply; 13+ messages in thread
From: Ivan Khoronzhuk @ 2014-10-20 15:41 UTC (permalink / raw)
To: u-boot
On 10/20/2014 06:13 PM, Tom Rini wrote:
> On Wed, Oct 15, 2014 at 02:55:28AM +0300, Ivan Khoronzhuk wrote:
>
>> From: Hao Zhang <hzhang@ti.com>
>>
>> This patch adds clock definitions and commands to support Keystone II
>> K2L SOC.
>>
>> Acked-by: Vitaly Andrianov <vitalya@ti.com>
>> Signed-off-by: Hao Zhang <hzhang@ti.com>
>> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
> [snip]
>> diff --git a/arch/arm/cpu/armv7/keystone/cmd_clock.c b/arch/arm/cpu/armv7/keystone/cmd_clock.c
>> index d97c95b..9204887 100644
>> --- a/arch/arm/cpu/armv7/keystone/cmd_clock.c
>> +++ b/arch/arm/cpu/armv7/keystone/cmd_clock.c
>> @@ -72,6 +72,13 @@ U_BOOT_CMD(
>> "<pa|ddr3> <mult> <div> <OD>\n"
>> );
>> #endif
>> +#ifdef CONFIG_SOC_K2L
>> +U_BOOT_CMD(
>> + pllset, 5, 0, do_pll_cmd,
>> + "set pll multiplier and pre divider",
>> + "<pa|arm|ddr3> <mult> <div> <OD>\n"
>> +);
>> +#endif
>>
>> int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
>> {
>> @@ -101,6 +108,9 @@ U_BOOT_CMD(
>> #ifdef CONFIG_SOC_K2E
>> "See the 'enum clk_e' in the clock-k2e.h for clk indexes\n"
>> #endif
>> +#ifdef CONFIG_SOC_K2L
>> + "See the 'enum clk_e' in the clock-k2l.h for clk indexes\n"
>> +#endif
>> );
> I'm not going to block on all of this duplication, but we need to think
> how to do this cleaner so that the next K2 variant doesn't expand this
> mess further. Thanks!
>
I'll correct it to one line:
"See the 'enum clk_e' in the clock-k2*.h for clk indexes\n"
--
Regards,
Ivan Khoronzhuk
^ permalink raw reply [flat|nested] 13+ messages in thread* [U-Boot] [U-boot] [Patch v4 2/6] keystone2: clock: add K2L clock definitions and commands
2014-10-20 15:41 ` Ivan Khoronzhuk
@ 2014-10-20 15:55 ` Tom Rini
2014-10-22 13:51 ` Ivan Khoronzhuk
0 siblings, 1 reply; 13+ messages in thread
From: Tom Rini @ 2014-10-20 15:55 UTC (permalink / raw)
To: u-boot
On Mon, Oct 20, 2014 at 06:41:29PM +0300, Ivan Khoronzhuk wrote:
> On 10/20/2014 06:13 PM, Tom Rini wrote:
> >On Wed, Oct 15, 2014 at 02:55:28AM +0300, Ivan Khoronzhuk wrote:
> >
> >>From: Hao Zhang <hzhang@ti.com>
> >>
> >>This patch adds clock definitions and commands to support Keystone II
> >>K2L SOC.
> >>
> >>Acked-by: Vitaly Andrianov <vitalya@ti.com>
> >>Signed-off-by: Hao Zhang <hzhang@ti.com>
> >>Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
> >[snip]
> >>diff --git a/arch/arm/cpu/armv7/keystone/cmd_clock.c b/arch/arm/cpu/armv7/keystone/cmd_clock.c
> >>index d97c95b..9204887 100644
> >>--- a/arch/arm/cpu/armv7/keystone/cmd_clock.c
> >>+++ b/arch/arm/cpu/armv7/keystone/cmd_clock.c
> >>@@ -72,6 +72,13 @@ U_BOOT_CMD(
> >> "<pa|ddr3> <mult> <div> <OD>\n"
> >> );
> >> #endif
> >>+#ifdef CONFIG_SOC_K2L
> >>+U_BOOT_CMD(
> >>+ pllset, 5, 0, do_pll_cmd,
> >>+ "set pll multiplier and pre divider",
> >>+ "<pa|arm|ddr3> <mult> <div> <OD>\n"
> >>+);
> >>+#endif
> >> int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> >> {
> >>@@ -101,6 +108,9 @@ U_BOOT_CMD(
> >> #ifdef CONFIG_SOC_K2E
> >> "See the 'enum clk_e' in the clock-k2e.h for clk indexes\n"
> >> #endif
> >>+#ifdef CONFIG_SOC_K2L
> >>+ "See the 'enum clk_e' in the clock-k2l.h for clk indexes\n"
> >>+#endif
> >> );
> >I'm not going to block on all of this duplication, but we need to think
> >how to do this cleaner so that the next K2 variant doesn't expand this
> >mess further. Thanks!
> >
>
> I'll correct it to one line:
> "See the 'enum clk_e' in the clock-k2*.h for clk indexes\n"
That helps the second hunk, but still leaves the first. At some point,
even, we shouldn't say "go modify file foo" in the binary, that belongs
in board documentation. Like I said, this needs a little bit of
thinking.
--
Tom
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^ permalink raw reply [flat|nested] 13+ messages in thread* [U-Boot] [U-boot] [Patch v4 2/6] keystone2: clock: add K2L clock definitions and commands
2014-10-20 15:55 ` Tom Rini
@ 2014-10-22 13:51 ` Ivan Khoronzhuk
0 siblings, 0 replies; 13+ messages in thread
From: Ivan Khoronzhuk @ 2014-10-22 13:51 UTC (permalink / raw)
To: u-boot
On 10/20/2014 06:55 PM, Tom Rini wrote:
> On Mon, Oct 20, 2014 at 06:41:29PM +0300, Ivan Khoronzhuk wrote:
>> On 10/20/2014 06:13 PM, Tom Rini wrote:
>>> On Wed, Oct 15, 2014 at 02:55:28AM +0300, Ivan Khoronzhuk wrote:
>>>
>>>> From: Hao Zhang <hzhang@ti.com>
>>>>
>>>> This patch adds clock definitions and commands to support Keystone II
>>>> K2L SOC.
>>>>
>>>> Acked-by: Vitaly Andrianov <vitalya@ti.com>
>>>> Signed-off-by: Hao Zhang <hzhang@ti.com>
>>>> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
>>> [snip]
>>>> diff --git a/arch/arm/cpu/armv7/keystone/cmd_clock.c b/arch/arm/cpu/armv7/keystone/cmd_clock.c
>>>> index d97c95b..9204887 100644
>>>> --- a/arch/arm/cpu/armv7/keystone/cmd_clock.c
>>>> +++ b/arch/arm/cpu/armv7/keystone/cmd_clock.c
>>>> @@ -72,6 +72,13 @@ U_BOOT_CMD(
>>>> "<pa|ddr3> <mult> <div> <OD>\n"
>>>> );
>>>> #endif
>>>> +#ifdef CONFIG_SOC_K2L
>>>> +U_BOOT_CMD(
>>>> + pllset, 5, 0, do_pll_cmd,
>>>> + "set pll multiplier and pre divider",
>>>> + "<pa|arm|ddr3> <mult> <div> <OD>\n"
>>>> +);
>>>> +#endif
>>>> int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
>>>> {
>>>> @@ -101,6 +108,9 @@ U_BOOT_CMD(
>>>> #ifdef CONFIG_SOC_K2E
>>>> "See the 'enum clk_e' in the clock-k2e.h for clk indexes\n"
>>>> #endif
>>>> +#ifdef CONFIG_SOC_K2L
>>>> + "See the 'enum clk_e' in the clock-k2l.h for clk indexes\n"
>>>> +#endif
>>>> );
>>> I'm not going to block on all of this duplication, but we need to think
>>> how to do this cleaner so that the next K2 variant doesn't expand this
>>> mess further. Thanks!
>>>
>> I'll correct it to one line:
>> "See the 'enum clk_e' in the clock-k2*.h for clk indexes\n"
> That helps the second hunk, but still leaves the first. At some point,
> even, we shouldn't say "go modify file foo" in the binary, that belongs
> in board documentation. Like I said, this needs a little bit of
> thinking.
>
Tom,
the series is updated according to your propositions:
"[U-boot] [Patch v6 0/6] keystone2: add k2l SoC and k2l_evm board support"
https://www.mail-archive.com/u-boot at lists.denx.de/msg150727.html
It's based on patch that corrects command usage descriptions:
"[U-Boot,U-boot] ARM: cmd_clock: generalize command usage description"
http://patchwork.ozlabs.org/patch/402102/
I've sent it separately to not mix it with K2L support series.
Thanks!
--
Regards,
Ivan Khoronzhuk
^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [U-boot] [Patch v4 3/6] keystone2: msmc: add MSMC cache coherency support for K2L SOC
2014-10-14 23:55 [U-Boot] [U-boot] [Patch v4 0/6] keystone2: add k2l SoC and k2l_evm board support Ivan Khoronzhuk
2014-10-14 23:55 ` [U-Boot] [U-boot] [Patch v4 1/6] ARM: keystone2: add K2L device hardware definitions Ivan Khoronzhuk
2014-10-14 23:55 ` [U-Boot] [U-boot] [Patch v4 2/6] keystone2: clock: add K2L clock definitions and commands Ivan Khoronzhuk
@ 2014-10-14 23:55 ` Ivan Khoronzhuk
2014-10-20 15:13 ` Tom Rini
2014-10-14 23:55 ` [U-Boot] [U-boot] [Patch v4 4/6] ARM: keystone2: spl: add K2L SoC support Ivan Khoronzhuk
` (2 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Ivan Khoronzhuk @ 2014-10-14 23:55 UTC (permalink / raw)
To: u-boot
From: Hao Zhang <hzhang@ti.com>
This patch adds Keystone II Lamar (K2L) SoC specific definitions
to support MSMC cache coherency.
Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
---
arch/arm/cpu/armv7/keystone/init.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/cpu/armv7/keystone/init.c
index a8f8aee..a0ecfa2 100644
--- a/arch/arm/cpu/armv7/keystone/init.c
+++ b/arch/arm/cpu/armv7/keystone/init.c
@@ -32,6 +32,9 @@ int arch_cpu_init(void)
#ifdef CONFIG_SOC_K2E
msmc_share_all_segments(13); /* PCIE 1 */
#endif
+#ifdef CONFIG_SOC_K2L
+ msmc_share_all_segments(14); /* PCIE 1 */
+#endif
/*
* just initialise the COM2 port so that TI specific
--
1.8.3.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* [U-Boot] [U-boot] [Patch v4 3/6] keystone2: msmc: add MSMC cache coherency support for K2L SOC
2014-10-14 23:55 ` [U-Boot] [U-boot] [Patch v4 3/6] keystone2: msmc: add MSMC cache coherency support for K2L SOC Ivan Khoronzhuk
@ 2014-10-20 15:13 ` Tom Rini
2014-10-20 15:20 ` Ivan Khoronzhuk
0 siblings, 1 reply; 13+ messages in thread
From: Tom Rini @ 2014-10-20 15:13 UTC (permalink / raw)
To: u-boot
On Wed, Oct 15, 2014 at 02:55:29AM +0300, Ivan Khoronzhuk wrote:
> From: Hao Zhang <hzhang@ti.com>
>
> This patch adds Keystone II Lamar (K2L) SoC specific definitions
> to support MSMC cache coherency.
>
> Acked-by: Vitaly Andrianov <vitalya@ti.com>
> Signed-off-by: Hao Zhang <hzhang@ti.com>
> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
> ---
> arch/arm/cpu/armv7/keystone/init.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/cpu/armv7/keystone/init.c
> index a8f8aee..a0ecfa2 100644
> --- a/arch/arm/cpu/armv7/keystone/init.c
> +++ b/arch/arm/cpu/armv7/keystone/init.c
> @@ -32,6 +32,9 @@ int arch_cpu_init(void)
> #ifdef CONFIG_SOC_K2E
> msmc_share_all_segments(13); /* PCIE 1 */
> #endif
> +#ifdef CONFIG_SOC_K2L
> + msmc_share_all_segments(14); /* PCIE 1 */
> +#endif
>
> /*
> * just initialise the COM2 port so that TI specific
Where does 13/14 come from and can we just define what that means in a
K2-foo specific header so we can always do
msmc_share_all_segments(K2_MSMC_SEGMENTS_NR) or whatever? Thanks!
--
Tom
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^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [U-boot] [Patch v4 3/6] keystone2: msmc: add MSMC cache coherency support for K2L SOC
2014-10-20 15:13 ` Tom Rini
@ 2014-10-20 15:20 ` Ivan Khoronzhuk
0 siblings, 0 replies; 13+ messages in thread
From: Ivan Khoronzhuk @ 2014-10-20 15:20 UTC (permalink / raw)
To: u-boot
On 10/20/2014 06:13 PM, Tom Rini wrote:
> On Wed, Oct 15, 2014 at 02:55:29AM +0300, Ivan Khoronzhuk wrote:
>> From: Hao Zhang <hzhang@ti.com>
>>
>> This patch adds Keystone II Lamar (K2L) SoC specific definitions
>> to support MSMC cache coherency.
>>
>> Acked-by: Vitaly Andrianov <vitalya@ti.com>
>> Signed-off-by: Hao Zhang <hzhang@ti.com>
>> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
>> ---
>> arch/arm/cpu/armv7/keystone/init.c | 3 +++
>> 1 file changed, 3 insertions(+)
>>
>> diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/cpu/armv7/keystone/init.c
>> index a8f8aee..a0ecfa2 100644
>> --- a/arch/arm/cpu/armv7/keystone/init.c
>> +++ b/arch/arm/cpu/armv7/keystone/init.c
>> @@ -32,6 +32,9 @@ int arch_cpu_init(void)
>> #ifdef CONFIG_SOC_K2E
>> msmc_share_all_segments(13); /* PCIE 1 */
>> #endif
>> +#ifdef CONFIG_SOC_K2L
>> + msmc_share_all_segments(14); /* PCIE 1 */
>> +#endif
>>
>> /*
>> * just initialise the COM2 port so that TI specific
> Where does 13/14 come from and can we just define what that means in a
> K2-foo specific header so we can always do
> msmc_share_all_segments(K2_MSMC_SEGMENTS_NR) or whatever? Thanks!
>
Ok, I will update it.
But, currently, there is newer version,
[U-boot] [Patch v5 0/6] keystone2: add k2l SoC and k2l_evm board support
https://www.mail-archive.com/u-boot at lists.denx.de/msg150245.html
--
Regards,
Ivan Khoronzhuk
^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [U-boot] [Patch v4 4/6] ARM: keystone2: spl: add K2L SoC support
2014-10-14 23:55 [U-Boot] [U-boot] [Patch v4 0/6] keystone2: add k2l SoC and k2l_evm board support Ivan Khoronzhuk
` (2 preceding siblings ...)
2014-10-14 23:55 ` [U-Boot] [U-boot] [Patch v4 3/6] keystone2: msmc: add MSMC cache coherency support for K2L SOC Ivan Khoronzhuk
@ 2014-10-14 23:55 ` Ivan Khoronzhuk
2014-10-14 23:55 ` [U-Boot] [U-boot] [Patch v4 5/6] keystone2: enable OSR clock domain for K2L SoC Ivan Khoronzhuk
2014-10-14 23:55 ` [U-Boot] [U-boot] [Patch v4 6/6] keystone2: k2l-evm: add board support Ivan Khoronzhuk
5 siblings, 0 replies; 13+ messages in thread
From: Ivan Khoronzhuk @ 2014-10-14 23:55 UTC (permalink / raw)
To: u-boot
From: Hao Zhang <hzhang@ti.com>
Add Keystone II Lamar (K2L) SoC support.
Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
---
arch/arm/cpu/armv7/keystone/spl.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/cpu/armv7/keystone/spl.c b/arch/arm/cpu/armv7/keystone/spl.c
index d4b0e9b..6a3adf4 100644
--- a/arch/arm/cpu/armv7/keystone/spl.c
+++ b/arch/arm/cpu/armv7/keystone/spl.c
@@ -31,6 +31,13 @@ static struct pll_init_data spl_pll_config[] = {
};
#endif
+#ifdef CONFIG_K2L_EVM
+static struct pll_init_data spl_pll_config[] = {
+ CORE_PLL_799,
+ TETRIS_PLL_491,
+};
+#endif
+
void spl_init_keystone_plls(void)
{
init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
--
1.8.3.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* [U-Boot] [U-boot] [Patch v4 5/6] keystone2: enable OSR clock domain for K2L SoC
2014-10-14 23:55 [U-Boot] [U-boot] [Patch v4 0/6] keystone2: add k2l SoC and k2l_evm board support Ivan Khoronzhuk
` (3 preceding siblings ...)
2014-10-14 23:55 ` [U-Boot] [U-boot] [Patch v4 4/6] ARM: keystone2: spl: add K2L SoC support Ivan Khoronzhuk
@ 2014-10-14 23:55 ` Ivan Khoronzhuk
2014-10-14 23:55 ` [U-Boot] [U-boot] [Patch v4 6/6] keystone2: k2l-evm: add board support Ivan Khoronzhuk
5 siblings, 0 replies; 13+ messages in thread
From: Ivan Khoronzhuk @ 2014-10-14 23:55 UTC (permalink / raw)
To: u-boot
From: Hao Zhang <hzhang@ti.com>
This patches enables the On-chip Shared Ram clock domain for K2L SoC.
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
---
arch/arm/cpu/armv7/keystone/init.c | 49 +++++++++++++++++++++++
arch/arm/include/asm/arch-keystone/hardware-k2l.h | 25 ++++++++++++
arch/arm/include/asm/arch-keystone/hardware.h | 1 +
3 files changed, 75 insertions(+)
diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/cpu/armv7/keystone/init.c
index a0ecfa2..2228132 100644
--- a/arch/arm/cpu/armv7/keystone/init.c
+++ b/arch/arm/cpu/armv7/keystone/init.c
@@ -13,6 +13,7 @@
#include <asm/arch/msmc.h>
#include <asm/arch/clock.h>
#include <asm/arch/hardware.h>
+#include <asm/arch/psc_defs.h>
void chip_configuration_unlock(void)
{
@@ -20,6 +21,53 @@ void chip_configuration_unlock(void)
__raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
}
+#ifdef CONFIG_SOC_K2L
+void osr_init(void)
+{
+ u32 i;
+ u32 j;
+ u32 val;
+ u32 base = KS2_OSR_CFG_BASE;
+ u32 ecc_ctrl[KS2_OSR_NUM_RAM_BANKS];
+
+ /* Enable the OSR clock domain */
+ psc_enable_module(KS2_LPSC_OSR);
+
+ /* Disable OSR ECC check for all the ram banks */
+ for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++) {
+ val = i | KS2_OSR_ECC_VEC_TRIG_RD |
+ (KS2_OSR_ECC_CTRL << KS2_OSR_ECC_VEC_RD_ADDR_SH);
+
+ writel(val , base + KS2_OSR_ECC_VEC);
+
+ /**
+ * wait till read is done.
+ * Print should be added after earlyprintk support is added.
+ */
+ for (j = 0; j < 10000; j++) {
+ val = readl(base + KS2_OSR_ECC_VEC);
+ if (val & KS2_OSR_ECC_VEC_RD_DONE)
+ break;
+ }
+
+ ecc_ctrl[i] = readl(base + KS2_OSR_ECC_CTRL) ^
+ KS2_OSR_ECC_CTRL_CHK;
+
+ writel(ecc_ctrl[i], KS2_MSMC_DATA_BASE + i * 4);
+ writel(ecc_ctrl[i], base + KS2_OSR_ECC_CTRL);
+ }
+
+ /* Reset OSR memory to all zeros */
+ for (i = 0; i < KS2_OSR_SIZE; i += 4)
+ writel(0, KS2_OSR_DATA_BASE + i);
+
+ /* Enable OSR ECC check for all the ram banks */
+ for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++)
+ writel(ecc_ctrl[i] |
+ KS2_OSR_ECC_CTRL_CHK, base + KS2_OSR_ECC_CTRL);
+}
+#endif
+
int arch_cpu_init(void)
{
chip_configuration_unlock();
@@ -34,6 +82,7 @@ int arch_cpu_init(void)
#endif
#ifdef CONFIG_SOC_K2L
msmc_share_all_segments(14); /* PCIE 1 */
+ osr_init();
#endif
/*
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2l.h b/arch/arm/include/asm/arch-keystone/hardware-k2l.h
index 3402d0c..dfde040 100644
--- a/arch/arm/include/asm/arch-keystone/hardware-k2l.h
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2l.h
@@ -57,6 +57,31 @@
#define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3
#define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D
+/* OSR */
+#define KS2_OSR_DATA_BASE 0x70000000 /* OSR data base */
+#define KS2_OSR_CFG_BASE 0x02348c00 /* OSR config base */
+#define KS2_OSR_ECC_VEC 0x08 /* ECC Vector reg */
+#define KS2_OSR_ECC_CTRL 0x14 /* ECC control reg */
+
+/* OSR ECC Vector register */
+#define KS2_OSR_ECC_VEC_TRIG_RD BIT(15) /* trigger a read op */
+#define KS2_OSR_ECC_VEC_RD_DONE BIT(24) /* read complete */
+
+#define KS2_OSR_ECC_VEC_RAM_ID_SH 0 /* RAM ID shift */
+#define KS2_OSR_ECC_VEC_RD_ADDR_SH 16 /* read address shift */
+
+/* OSR ECC control register */
+#define KS2_OSR_ECC_CTRL_EN BIT(0) /* ECC enable bit */
+#define KS2_OSR_ECC_CTRL_CHK BIT(1) /* ECC check bit */
+#define KS2_OSR_ECC_CTRL_RMW BIT(2) /* ECC check bit */
+
+/* Number of OSR RAM banks */
+#define KS2_OSR_NUM_RAM_BANKS 4
+
+/* OSR memory size */
+#define KS2_OSR_SIZE 0x100000
+
+
/* Number of DSP cores */
#define KS2_NUM_DSPS 4
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h
index adae69e..29f7bf1 100644
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -163,6 +163,7 @@ typedef volatile unsigned int *dv_reg_p;
/* MSMC control */
#define KS2_MSMC_CTRL_BASE 0x0bc00000
+#define KS2_MSMC_DATA_BASE 0x0c000000
/* USB */
#define KS2_USB_SS_BASE 0x02680000
--
1.8.3.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* [U-Boot] [U-boot] [Patch v4 6/6] keystone2: k2l-evm: add board support
2014-10-14 23:55 [U-Boot] [U-boot] [Patch v4 0/6] keystone2: add k2l SoC and k2l_evm board support Ivan Khoronzhuk
` (4 preceding siblings ...)
2014-10-14 23:55 ` [U-Boot] [U-boot] [Patch v4 5/6] keystone2: enable OSR clock domain for K2L SoC Ivan Khoronzhuk
@ 2014-10-14 23:55 ` Ivan Khoronzhuk
5 siblings, 0 replies; 13+ messages in thread
From: Ivan Khoronzhuk @ 2014-10-14 23:55 UTC (permalink / raw)
To: u-boot
From: Hao Zhang <hzhang@ti.com>
This patch adds Keystone II Lammar (K2L) EVM board support.
Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
---
arch/arm/cpu/armv7/keystone/Kconfig | 3 ++
arch/arm/include/asm/arch-keystone/clock-k2l.h | 6 +++
board/ti/ks2_evm/Kconfig | 16 +++++++
board/ti/ks2_evm/MAINTAINERS | 2 +
board/ti/ks2_evm/Makefile | 2 +
board/ti/ks2_evm/board_k2l.c | 60 ++++++++++++++++++++++++++
board/ti/ks2_evm/ddr3_cfg.c | 36 ++++++++++++++++
board/ti/ks2_evm/ddr3_cfg.h | 3 ++
board/ti/ks2_evm/ddr3_k2l.c | 43 ++++++++++++++++++
configs/k2l_evm_defconfig | 4 ++
include/configs/k2l_evm.h | 37 ++++++++++++++++
11 files changed, 212 insertions(+)
create mode 100644 board/ti/ks2_evm/board_k2l.c
create mode 100644 board/ti/ks2_evm/ddr3_k2l.c
create mode 100644 configs/k2l_evm_defconfig
create mode 100644 include/configs/k2l_evm.h
diff --git a/arch/arm/cpu/armv7/keystone/Kconfig b/arch/arm/cpu/armv7/keystone/Kconfig
index 24d0cbe..91211fd 100644
--- a/arch/arm/cpu/armv7/keystone/Kconfig
+++ b/arch/arm/cpu/armv7/keystone/Kconfig
@@ -9,6 +9,9 @@ config TARGET_K2HK_EVM
config TARGET_K2E_EVM
bool "TI Keystone 2 Edison EVM"
+config TARGET_K2L_EVM
+ bool "TI Keystone 2 Lamar EVM"
+
endchoice
config SYS_CPU
diff --git a/arch/arm/include/asm/arch-keystone/clock-k2l.h b/arch/arm/include/asm/arch-keystone/clock-k2l.h
index 8cacee0..b3f4e71 100644
--- a/arch/arm/include/asm/arch-keystone/clock-k2l.h
+++ b/arch/arm/include/asm/arch-keystone/clock-k2l.h
@@ -69,7 +69,9 @@ enum {
#define CORE_PLL_799 {CORE_PLL, 13, 1, 2}
#define CORE_PLL_983 {CORE_PLL, 16, 1, 2}
+#define CORE_PLL_1000 {CORE_PLL, 114, 7, 2}
#define CORE_PLL_1167 {CORE_PLL, 19, 1, 2}
+#define CORE_PLL_1198 {CORE_PLL, 39, 2, 2}
#define CORE_PLL_1228 {CORE_PLL, 20, 1, 2}
#define PASS_PLL_1228 {PASS_PLL, 20, 1, 2}
#define PASS_PLL_983 {PASS_PLL, 16, 1, 2}
@@ -78,8 +80,12 @@ enum {
#define TETRIS_PLL_737 {TETRIS_PLL, 12, 1, 2}
#define TETRIS_PLL_799 {TETRIS_PLL, 13, 1, 2}
#define TETRIS_PLL_983 {TETRIS_PLL, 16, 1, 2}
+#define TETRIS_PLL_1000 {TETRIS_PLL, 114, 7, 2}
#define TETRIS_PLL_1167 {TETRIS_PLL, 19, 1, 2}
+#define TETRIS_PLL_1198 {TETRIS_PLL, 39, 2, 2}
#define TETRIS_PLL_1228 {TETRIS_PLL, 20, 1, 2}
+#define TETRIS_PLL_1352 {TETRIS_PLL, 22, 1, 2}
+#define TETRIS_PLL_1401 {TETRIS_PLL, 114, 5, 2}
#define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2}
#define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4}
#define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2}
diff --git a/board/ti/ks2_evm/Kconfig b/board/ti/ks2_evm/Kconfig
index 3108782..36c31ff 100644
--- a/board/ti/ks2_evm/Kconfig
+++ b/board/ti/ks2_evm/Kconfig
@@ -29,3 +29,19 @@ config SYS_CONFIG_NAME
default "k2hk_evm"
endif
+
+if TARGET_K2L_EVM
+
+config SYS_BOARD
+ string
+ default "ks2_evm"
+
+config SYS_VENDOR
+ string
+ default "ti"
+
+config SYS_CONFIG_NAME
+ string
+ default "k2l_evm"
+
+endif
diff --git a/board/ti/ks2_evm/MAINTAINERS b/board/ti/ks2_evm/MAINTAINERS
index 595a80a..87c36c9 100644
--- a/board/ti/ks2_evm/MAINTAINERS
+++ b/board/ti/ks2_evm/MAINTAINERS
@@ -6,3 +6,5 @@ F: include/configs/k2hk_evm.h
F: configs/k2hk_evm_defconfig
F: include/configs/k2e_evm.h
F: configs/k2e_evm_defconfig
+F: include/configs/k2l_evm.h
+F: configs/k2l_evm_defconfig
diff --git a/board/ti/ks2_evm/Makefile b/board/ti/ks2_evm/Makefile
index 00f1164..071dbee 100644
--- a/board/ti/ks2_evm/Makefile
+++ b/board/ti/ks2_evm/Makefile
@@ -11,3 +11,5 @@ obj-$(CONFIG_K2HK_EVM) += board_k2hk.o
obj-$(CONFIG_K2HK_EVM) += ddr3_k2hk.o
obj-$(CONFIG_K2E_EVM) += board_k2e.o
obj-$(CONFIG_K2E_EVM) += ddr3_k2e.o
+obj-$(CONFIG_K2L_EVM) += board_k2l.o
+obj-$(CONFIG_K2L_EVM) += ddr3_k2l.o
diff --git a/board/ti/ks2_evm/board_k2l.c b/board/ti/ks2_evm/board_k2l.c
new file mode 100644
index 0000000..b8faff6
--- /dev/null
+++ b/board/ti/ks2_evm/board_k2l.c
@@ -0,0 +1,60 @@
+/*
+ * K2L EVM : Board initialization
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/ddr3.h>
+#include <asm/arch/hardware.h>
+#include <asm/ti-common/ti-aemif.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned int external_clk[ext_clk_count] = {
+ [sys_clk] = 122880000,
+ [alt_core_clk] = 100000000,
+ [pa_clk] = 122880000,
+ [tetris_clk] = 122880000,
+ [ddr3_clk] = 100000000,
+ [pcie_clk] = 100000000,
+ [sgmii_clk] = 156250000,
+ [usb_clk] = 100000000,
+};
+
+static struct pll_init_data core_pll_config[] = {
+ CORE_PLL_799,
+ CORE_PLL_1000,
+ CORE_PLL_1198,
+};
+
+static struct pll_init_data tetris_pll_config[] = {
+ TETRIS_PLL_799,
+ TETRIS_PLL_1000,
+ TETRIS_PLL_1198,
+ TETRIS_PLL_1352,
+ TETRIS_PLL_1401,
+};
+
+static struct pll_init_data pa_pll_config =
+ PASS_PLL_983;
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+ int speed;
+
+ speed = get_max_dev_speed();
+ init_pll(&core_pll_config[speed]);
+
+ init_pll(&pa_pll_config);
+
+ speed = get_max_arm_speed();
+ init_pll(&tetris_pll_config[speed]);
+
+ return 0;
+}
+#endif
diff --git a/board/ti/ks2_evm/ddr3_cfg.c b/board/ti/ks2_evm/ddr3_cfg.c
index f7da9f2..ab44676 100644
--- a/board/ti/ks2_evm/ddr3_cfg.c
+++ b/board/ti/ks2_evm/ddr3_cfg.c
@@ -133,6 +133,42 @@ struct ddr3_emif_config ddr3_1600_4g = {
};
#endif
+struct ddr3_phy_config ddr3phy_1600_2g = {
+ .pllcr = 0x0001C000ul,
+ .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
+ .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
+ .ptr0 = 0x42C21590ul,
+ .ptr1 = 0xD05612C0ul,
+ .ptr2 = 0, /* not set in gel */
+ .ptr3 = 0x0D861A80ul,
+ .ptr4 = 0x0C827100ul,
+ .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
+ .dcr_val = ((1 << 10)),
+ .dtpr0 = 0x9D5CBB66ul,
+ .dtpr1 = 0x12868300ul,
+ .dtpr2 = 0x5002D200ul,
+ .mr0 = 0x00001C70ul,
+ .mr1 = 0x00000006ul,
+ .mr2 = 0x00000018ul,
+ .dtcr = 0x710035C7ul,
+ .pgcr2 = 0x00F07A12ul,
+ .zq0cr1 = 0x0001005Dul,
+ .zq1cr1 = 0x0001005Bul,
+ .zq2cr1 = 0x0001005Bul,
+ .pir_v1 = 0x00000033ul,
+ .pir_v2 = 0x0000FF81ul,
+};
+
+struct ddr3_emif_config ddr3_1600_2g = {
+ .sdcfg = 0x6200CE62ul,
+ .sdtim1 = 0x166C9855ul,
+ .sdtim2 = 0x00001D4Aul,
+ .sdtim3 = 0x435DFF53ul,
+ .sdtim4 = 0x543F0CFFul,
+ .zqcfg = 0x70073200ul,
+ .sdrfc = 0x00001869ul,
+};
+
int ddr3_get_dimm_params(char *dimm_name)
{
int ret;
diff --git a/board/ti/ks2_evm/ddr3_cfg.h b/board/ti/ks2_evm/ddr3_cfg.h
index 15fcf52..5bd786c 100644
--- a/board/ti/ks2_evm/ddr3_cfg.h
+++ b/board/ti/ks2_evm/ddr3_cfg.h
@@ -19,6 +19,9 @@ extern struct ddr3_emif_config ddr3_1333_2g;
extern struct ddr3_phy_config ddr3phy_1600_4g;
extern struct ddr3_emif_config ddr3_1600_4g;
+extern struct ddr3_phy_config ddr3phy_1600_2g;
+extern struct ddr3_emif_config ddr3_1600_2g;
+
int ddr3_get_dimm_params(char *dimm_name);
#endif /* __DDR3_CFG_H */
diff --git a/board/ti/ks2_evm/ddr3_k2l.c b/board/ti/ks2_evm/ddr3_k2l.c
new file mode 100644
index 0000000..98da162
--- /dev/null
+++ b/board/ti/ks2_evm/ddr3_k2l.c
@@ -0,0 +1,43 @@
+/*
+ * Keystone2: DDR3 initialization
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include "ddr3_cfg.h"
+#include <asm/arch/ddr3.h>
+
+static int ddr3_size;
+static struct pll_init_data ddr3_400 = DDR3_PLL_400;
+
+void ddr3_init(void)
+{
+ char dimm_name[32];
+
+ ddr3_get_dimm_params(dimm_name);
+ printf("Detected SO-DIMM [%s]\n", dimm_name);
+
+ init_pll(&ddr3_400);
+
+ /* No SO-DIMM, 2GB discreet DDR */
+ printf("DRAM: 2 GiB\n");
+ ddr3_size = 2;
+
+ /* Reset DDR3 PHY after PLL enabled */
+ ddr3_reset_ddrphy();
+
+ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_2g);
+ ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_2g);
+}
+
+/**
+ * ddr3_get_size - return ddr3 size in GiB
+ */
+int ddr3_get_size(void)
+{
+ return ddr3_size;
+}
diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
new file mode 100644
index 0000000..45399ce
--- /dev/null
+++ b/configs/k2l_evm_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SPL=y
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_KEYSTONE=y
++S:CONFIG_TARGET_K2L_EVM=y
diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h
new file mode 100644
index 0000000..0e1f725
--- /dev/null
+++ b/include/configs/k2l_evm.h
@@ -0,0 +1,37 @@
+/*
+ * Configuration header file for TI's k2l-evm
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_K2L_EVM_H
+#define __CONFIG_K2L_EVM_H
+
+/* Platform type */
+#define CONFIG_SOC_K2L
+#define CONFIG_K2L_EVM
+
+/* U-Boot general configuration */
+#define CONFIG_SYS_PROMPT "K2L EVM # "
+
+#define KS2_ARGS_UBI "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "\
+ "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,4096\0"
+
+#define KS2_FDT_NAME "name_fdt=k2l-evm.dtb\0"
+#define KS2_ADDR_MON "addr_mon=0x0c140000\0"
+#define KS2_NAME_MON "name_mon=skern-k2l-evm.bin\0"
+#define NAME_UBOOT "name_uboot=u-boot-spi-k2l-evm.gph\0"
+#define NAME_UBI "name_ubi=k2l-evm-ubifs.ubi\0"
+
+#include <configs/ks2_evm.h>
+
+/* SPL SPI Loader Configuration */
+#define CONFIG_SPL_TEXT_BASE 0x0c100000
+
+/* NAND Configuration */
+#define CONFIG_SYS_NAND_PAGE_4K
+
+#endif /* __CONFIG_K2L_EVM_H */
--
1.8.3.2
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