[U-Boot] [PATCH] mx6sabresd: Move the DCD settings to spl code

Fabio Estevam
2014-11-13T21:58:33Z

From: Fabio Estevam <fabio.estevam@freescale.com>

mx6sabresd_spl.cfg configures CCM registers, GPR registers and CCM_CCOSR.

Move the configuration to the spl code.

CCM_CCOSR setting is no longer required to get audio functionality in the
kernel, so remove such setting.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
Hi Stefano,

Actually I would like to get rid of mx6sabresd_spl.cfg completely, but when
I tried to remove it, I ended up with SPL not being built.

Any suggestions?

board/freescale/mx6sabresd/mx6sabresd.c | 27 +++++++++++++++++++
board/freescale/mx6sabresd/mx6sabresd_spl.cfg | 38 ---------------------------
2 files changed, 27 insertions(+), 38 deletions(-)

diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index 1142e8a..343c3b6 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -729,6 +729,30 @@ static struct mx6_ddr3_cfg mem_ddr = {
.trasmin = 3500,
};

+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0x00C03F3F, &ccm->CCGR0);
+ writel(0x0030FC03, &ccm->CCGR1);
+ writel(0x0FFFC000, &ccm->CCGR2);
+ writel(0x3FF00000, &ccm->CCGR3);
+ writel(0x00FFF300, &ccm->CCGR4);
+ writel(0x0F0000C3, &ccm->CCGR5);
+ writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void gpr_init(void)
+{
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ /* enable AXI cache for VDOA/VPU/IPU */
+ writel(0xF00000CF, &iomux->gpr[4]);
+ /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+ writel(0x007F007F, &iomux->gpr[6]);
+ writel(0x007F007F, &iomux->gpr[7]);
+}
+
/*
* This section require the differentiation
* between iMX6 Sabre Families.
@@ -768,6 +792,9 @@ void board_init_f(ulong dummy)
/* setup AIPS and disable watchdog */
arch_cpu_init();

+ ccgr_init();
+ gpr_init();
+
/* iomux and setup of i2c */
board_early_init_f();

diff --git a/board/freescale/mx6sabresd/mx6sabresd_spl.cfg b/board/freescale/mx6sabresd/mx6sabresd_spl.cfg
index 2bf4817..1d031ba 100644
--- a/board/freescale/mx6sabresd/mx6sabresd_spl.cfg
+++ b/board/freescale/mx6sabresd/mx6sabresd_spl.cfg
@@ -18,41 +18,3 @@ IMAGE_VERSION 2
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM sd
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type Address Value
- *
- * where:
- * Addr-type register length (1,2 or 4 bytes)
- * Address absolute address of the register
- * value value to be stored in the register
- */
-
-/* set the default clock gate to save power */
-DATA 4 0x020c4068 0x00C03F3F
-DATA 4 0x020c406c 0x0030FC03
-DATA 4 0x020c4070 0x0FFFC000
-DATA 4 0x020c4074 0x3FF00000
-DATA 4 0x020c4078 0x00FFF300
-DATA 4 0x020c407c 0x0F0000C3
-DATA 4 0x020c4080 0x000003FF
-
-/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4 0x020e0010 0xF00000CF
-/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-DATA 4 0x020e0018 0x007F007F
-DATA 4 0x020e001c 0x007F007F
-
-/*
- * Setup CCM_CCOSR register as follows:
- *
- * cko1_en = 1 --> CKO1 enabled
- * cko1_div = 111 --> divide by 8
- * cko1_sel = 1011 --> ahb_clk_root
- *
- * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
- */
-DATA 4 0x020c4060 0x000000fb
--
1.9.1