* [U-Boot] [PATCH] t104xrdb: Add Errata A_007662, A_008007 workaround in pbi.cfg
@ 2014-09-17 10:27 Priyanka Jain
2014-11-14 21:27 ` York Sun
0 siblings, 1 reply; 2+ messages in thread
From: Priyanka Jain @ 2014-09-17 10:27 UTC (permalink / raw)
To: u-boot
-A_007662 states that for x1 link width, PCIe2 controller trains in
Gen1 speed while configured for Gen2 speed.
Workaround:Set the width to x1 and speed to Gen2 by writing to
CCSR registers in PBI phase
-A_008007 states that PVR register may show random value.
Workaround: Reset PVR register using DCSR space in PBI phase
Add PBI based software workaround for A_007662 and A_008007
in t104x_pbi.cfg. This is required for SPL-based bootloaders
like NAND-boot, SD-boot, SPI-boot
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
---
board/freescale/t104xrdb/t104x_pbi.cfg | 10 ++++++++++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/board/freescale/t104xrdb/t104x_pbi.cfg b/board/freescale/t104xrdb/t104x_pbi.cfg
index 7b9e9b0..b83b9b7 100644
--- a/board/freescale/t104xrdb/t104x_pbi.cfg
+++ b/board/freescale/t104xrdb/t104x_pbi.cfg
@@ -1,4 +1,14 @@
#PBI commands
+#Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed
+09250100 00000400
+09250108 00002000
+#Software Workaround for errata A-008007 to reset PVR register
+09000010 0000000b
+09000014 c0000000
+09000018 81d00017
+89020400 a1000000
+091380c0 000f0000
+89020400 00000000
#Initialize CPC1
09010000 00200400
09138000 00000000
--
1.7.4.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* [U-Boot] [PATCH] t104xrdb: Add Errata A_007662, A_008007 workaround in pbi.cfg
2014-09-17 10:27 [U-Boot] [PATCH] t104xrdb: Add Errata A_007662, A_008007 workaround in pbi.cfg Priyanka Jain
@ 2014-11-14 21:27 ` York Sun
0 siblings, 0 replies; 2+ messages in thread
From: York Sun @ 2014-11-14 21:27 UTC (permalink / raw)
To: u-boot
On 09/17/2014 03:27 AM, Priyanka Jain wrote:
> -A_007662 states that for x1 link width, PCIe2 controller trains in
> Gen1 speed while configured for Gen2 speed.
> Workaround:Set the width to x1 and speed to Gen2 by writing to
> CCSR registers in PBI phase
>
> -A_008007 states that PVR register may show random value.
> Workaround: Reset PVR register using DCSR space in PBI phase
>
> Add PBI based software workaround for A_007662 and A_008007
> in t104x_pbi.cfg. This is required for SPL-based bootloaders
> like NAND-boot, SD-boot, SPI-boot
>
> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
> ---
Applied to u-boot-mpc85xx master. Thanks.
York
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2014-09-17 10:27 [U-Boot] [PATCH] t104xrdb: Add Errata A_007662, A_008007 workaround in pbi.cfg Priyanka Jain
2014-11-14 21:27 ` York Sun
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