From mboxrd@z Thu Jan 1 00:00:00 1970 From: York Sun Date: Fri, 14 Nov 2014 13:27:26 -0800 Subject: [U-Boot] [PATCH] t104xrdb: Add Errata A_007662, A_008007 workaround in pbi.cfg In-Reply-To: <1410949674-15633-1-git-send-email-Priyanka.Jain@freescale.com> References: <1410949674-15633-1-git-send-email-Priyanka.Jain@freescale.com> Message-ID: <546673BE.4020801@freescale.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 09/17/2014 03:27 AM, Priyanka Jain wrote: > -A_007662 states that for x1 link width, PCIe2 controller trains in > Gen1 speed while configured for Gen2 speed. > Workaround:Set the width to x1 and speed to Gen2 by writing to > CCSR registers in PBI phase > > -A_008007 states that PVR register may show random value. > Workaround: Reset PVR register using DCSR space in PBI phase > > Add PBI based software workaround for A_007662 and A_008007 > in t104x_pbi.cfg. This is required for SPL-based bootloaders > like NAND-boot, SD-boot, SPI-boot > > Signed-off-by: Priyanka Jain > --- Applied to u-boot-mpc85xx master. Thanks. York