[U-Boot] [PATCH v3 3/3] arm: odroid: usb: add support for usb host including ethernet

Jaehoon Chung
2014-10-30T01:17:56Z

On 10/30/2014 01:22 AM, Suriyan Ramasami wrote:
> This change adds support for enabling the USB host features of the board.
> This includes the USB3503A hub and the SMC LAN9730 ethernet controller
> as well.
>
> Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com>
>
> ---
>
> Changes in v3:
> * removed set_usb_ethaddr() and related code as the GUID registers do not
> seem to be documented anywhere. This is sad, as this mechanism allows
> for each Odroid to boot up with the same MAC address every time, but no
> two odroids shall have the same MAC address on boot. This ensures multiple
> odroids in the same LAN to come up without conflicting MAC addresses.
> * Minkyu - Do not mix cpu_is... and proid_is...
>
> Changes in v2:
> * Jaehoon - Split power.[ch] as a separate patch
> * Removed an unneeded header file from ehci-exynos.c
> * Jaehoon - Fix indentation in the dts file
>
> Changes in v1:
> * First try
>
> arch/arm/dts/exynos4412-odroid.dts | 11 +++++++
> arch/arm/include/asm/arch-exynos/ehci.h | 13 ++++++++
> board/samsung/odroid/odroid.c | 32 +++++++++++++++++++
> drivers/usb/host/ehci-exynos.c | 55 ++++++++++++++++++++++++++++-----
> include/configs/odroid.h | 13 ++++++++
> 5 files changed, 116 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm/dts/exynos4412-odroid.dts b/arch/arm/dts/exynos4412-odroid.dts
> index 4c5e2b3..2df1801 100644
> --- a/arch/arm/dts/exynos4412-odroid.dts
> +++ b/arch/arm/dts/exynos4412-odroid.dts
> @@ -67,4 +67,15 @@
> div = <0x3>;
> index = <4>;
> };
> +
> + ehci at 12580000 {
> + compatible = "samsung,exynos-ehci";
> + reg = <0x12580000 0x100>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + phy {
> + compatible = "samsung,exynos-usb-phy";
> + reg = <0x125B0000 0x100>;
> + };
> + };
> };
> diff --git a/arch/arm/include/asm/arch-exynos/ehci.h b/arch/arm/include/asm/arch-exynos/ehci.h
> index d2d70bd..3800fa9 100644
> --- a/arch/arm/include/asm/arch-exynos/ehci.h
> +++ b/arch/arm/include/asm/arch-exynos/ehci.h
> @@ -12,6 +12,13 @@
>
> #define CLK_24MHZ 5
>
> +#define PHYPWR_NORMAL_MASK_PHY0 (0x39 << 0)
> +#define PHYPWR_NORMAL_MASK_PHY1 (0x7 << 6)
> +#define PHYPWR_NORMAL_MASK_HSIC0 (0x7 << 9)
> +#define PHYPWR_NORMAL_MASK_HSIC1 (0x7 << 12)
> +#define RSTCON_HOSTPHY_SWRST (0xf << 3)
> +#define RSTCON_SWRST (0x1 << 0)
> +
> #define HOST_CTRL0_PHYSWRSTALL (1 << 31)
> #define HOST_CTRL0_COMMONON_N (1 << 9)
> #define HOST_CTRL0_SIDDQ (1 << 6)
> @@ -61,6 +68,12 @@ struct exynos_usb_phy {
> unsigned int usbotgtune;
> };
>
> +struct exynos4412_usb_phy {
> + unsigned int usbphyctrl;
> + unsigned int usbphyclk;
> + unsigned int usbphyrstcon;
> +};
> +
> /* Switch on the VBUS power. */
> int board_usb_vbus_init(void);
>
> diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c
> index 5edb250..d671f13 100644
> --- a/board/samsung/odroid/odroid.c
> +++ b/board/samsung/odroid/odroid.c
> @@ -453,9 +453,41 @@ struct s3c_plat_otg_data s5pc210_otg_data = {
> .usb_phy_ctrl = EXYNOS4X12_USBPHY_CONTROL,
> .usb_flags = PHY0_SLEEP,
> };
> +#endif
> +
> +#if defined(CONFIG_USB_GADGET) || defined(CONFIG_CMD_USB)
>
> int board_usb_init(int index, enum usb_init_type init)
> {
> +#ifdef CONFIG_CMD_USB
> + struct pmic *p_pmic;
> +
> + /* Set Ref freq 0 => 24MHz, 1 => 26MHz*/
> + /* Odroid Us have it at 24MHz, Odroid Xs at 26MHz */
> + if (gd->board_type == ODROID_TYPE_U3)
> + gpio_direction_output(EXYNOS4X12_GPIO_X30, 0);
> + else
> + gpio_direction_output(EXYNOS4X12_GPIO_X30, 1);
> +
> + /* Disconnect, Reset, Connect */
> + gpio_direction_output(EXYNOS4X12_GPIO_X34, 0);
> + gpio_direction_output(EXYNOS4X12_GPIO_X35, 0);
> + gpio_direction_output(EXYNOS4X12_GPIO_X35, 1);
> + gpio_direction_output(EXYNOS4X12_GPIO_X34, 1);
> +
> + /* Power off and on BUCK8 for LAN9730 */
> + debug("LAN9730 - Turning power buck 8 OFF and ON.\n");
> +
> + p_pmic = pmic_get("MAX77686_PMIC");
> + if (p_pmic && !pmic_probe(p_pmic)) {
> + max77686_set_buck_mode(p_pmic, 8, OPMODE_OFF);
> + max77686_set_buck_voltage(p_pmic, 8, 750000);
> + max77686_set_buck_voltage(p_pmic, 8, 3300000);
> + max77686_set_buck_mode(p_pmic, 8, OPMODE_ON);
> + }
> +
> +#endif
> +
> debug("USB_udc_probe\n");
> return s3c_udc_probe(&s5pc210_otg_data);
> }
> diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c
> index edd91a8..6fdbf57 100644
> --- a/drivers/usb/host/ehci-exynos.c
> +++ b/drivers/usb/host/ehci-exynos.c
> @@ -85,15 +85,10 @@ static int exynos_usb_parse_dt(const void *blob, struct exynos_ehci *exynos)
> }
> #endif
>
> -/* Setup the EHCI host controller. */
> -static void setup_usb_phy(struct exynos_usb_phy *usb)
> +static void exynos5_setup_usb_phy(struct exynos_usb_phy *usb)
> {
> u32 hsic_ctrl;
>
> - set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN);
> -
> - set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN);
> -
> clrbits_le32(&usb->usbphyctrl0,
> HOST_CTRL0_FSEL_MASK |
> HOST_CTRL0_COMMONON_N |
> @@ -150,8 +145,34 @@ static void setup_usb_phy(struct exynos_usb_phy *usb)
> EHCICTRL_ENAINCR16);
> }
>
> -/* Reset the EHCI host controller. */
> -static void reset_usb_phy(struct exynos_usb_phy *usb)
> +static void exynos4412_setup_usb_phy(struct exynos4412_usb_phy *usb)
> +{
> + writel(CLK_24MHZ, &usb->usbphyclk);
> +
> + clrbits_le32(&usb->usbphyctrl, (PHYPWR_NORMAL_MASK_HSIC0 |
> + PHYPWR_NORMAL_MASK_HSIC1 | PHYPWR_NORMAL_MASK_PHY1 |
> + PHYPWR_NORMAL_MASK_PHY0));
> +
> + setbits_le32(&usb->usbphyrstcon, (RSTCON_HOSTPHY_SWRST | RSTCON_SWRST));
> + udelay(10);
> + clrbits_le32(&usb->usbphyrstcon, (RSTCON_HOSTPHY_SWRST | RSTCON_SWRST));
> +}
> +
> +static void setup_usb_phy(struct exynos_usb_phy *usb)
> +{

Well, I didn't know exactly. but i think this is something strange.
is it always bypassed the "struct exynos_usb_phy"?

And don't need to modify the below code into exynos_usb_parse_dt()?

/*
* Get the base address for usbphy from the device node
*/
exynos->usb = (struct exynos_usb_phy *)fdtdec_get_addr(blob, node,
"reg");
if (exynos->usb == NULL) {
debug("Can't get the usbphy register address\n");
return -ENXIO;
}

Best Regards,
Jaehoon Chung

> + set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN);
> +
> + set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN);
> +
> + if (cpu_is_exynos5())
> + exynos5_setup_usb_phy(usb);
> + else if (cpu_is_exynos4())
> + if (proid_is_exynos4412())
> + exynos4412_setup_usb_phy((struct exynos4412_usb_phy *)
> + usb);
> +}
> +
> +static void exynos5_reset_usb_phy(struct exynos_usb_phy *usb)
> {
> u32 hsic_ctrl;
>
> @@ -171,6 +192,24 @@ static void reset_usb_phy(struct exynos_usb_phy *usb)
>
> setbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
> setbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
> +}
> +
> +static void exynos4412_reset_usb_phy(struct exynos4412_usb_phy *usb)
> +{
> + setbits_le32(&usb->usbphyctrl, (PHYPWR_NORMAL_MASK_HSIC0 |
> + PHYPWR_NORMAL_MASK_HSIC1 | PHYPWR_NORMAL_MASK_PHY1 |
> + PHYPWR_NORMAL_MASK_PHY0));
> +}
> +
> +/* Reset the EHCI host controller. */
> +static void reset_usb_phy(struct exynos_usb_phy *usb)
> +{
> + if (cpu_is_exynos5())
> + exynos5_reset_usb_phy(usb);
> + else if (cpu_is_exynos4())
> + if (proid_is_exynos4412())
> + exynos4412_reset_usb_phy((struct exynos4412_usb_phy *)
> + usb);
>
> set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_DISABLE);
> }
> diff --git a/include/configs/odroid.h b/include/configs/odroid.h
> index b928af8..807e96b 100644
> --- a/include/configs/odroid.h
> +++ b/include/configs/odroid.h
> @@ -198,6 +198,19 @@
>
> #define CONFIG_CMD_GPIO
>
> +/* USB */
> +#define CONFIG_CMD_USB
> +#define CONFIG_USB_EHCI
> +#define CONFIG_USB_EHCI_EXYNOS
> +#define CONFIG_USB_STORAGE
> +
> +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
> +#define CONFIG_CMD_NET
> +#define CONFIG_CMD_PING
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_USB_HOST_ETHER
> +#define CONFIG_USB_ETHER_SMSC95XX
> +
> /*
> * Supported Odroid boards: X3, U3
> * TODO: Add Odroid X support
>