* [U-Boot] [PATCH 3/3] mx6qsabreauto: Add parallel NOR flash support
2014-11-14 13:27 [U-Boot] [PATCH 1/3] imx: consolidate set_chipselect_size function Fabio Estevam
2014-11-14 13:27 ` [U-Boot] [PATCH 2/3] mx6: add weim registers Fabio Estevam
@ 2014-11-14 13:27 ` Fabio Estevam
2014-11-20 9:38 ` Stefano Babic
2014-11-20 9:38 ` [U-Boot] [PATCH 1/3] imx: consolidate set_chipselect_size function Stefano Babic
2 siblings, 1 reply; 6+ messages in thread
From: Fabio Estevam @ 2014-11-14 13:27 UTC (permalink / raw)
To: u-boot
From: Fabio Estevam <fabio.estevam@freescale.com>
mx6sabreauto boards come with 32 MiB of parallel NOR flash.
Add support for it:
U-Boot 2015.01-rc1-18107-g1543636-dirty (Nov 14 2014 - 11:11:04)
CPU: Freescale i.MX6Q rev1.2 at 792 MHz
Reset cause: POR
Board: MX6Q-Sabreauto revA
I2C: ready
DRAM: 2 GiB
Flash: 32 MiB
NAND: 0 MiB
Due to pin conflict with I2C3, only define configure I2C3 IOMUX when flash is
not used.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
board/freescale/mx6qsabreauto/mx6qsabreauto.c | 80 ++++++++++++++++++++++++++-
include/configs/mx6qsabreauto.h | 10 ++++
2 files changed, 89 insertions(+), 1 deletion(-)
diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
index c35dcaf..15df171 100644
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -53,6 +53,10 @@ DECLARE_GLOBAL_DATA_PTR;
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -97,6 +101,7 @@ static struct i2c_pads_info i2c_pad_info1 = {
}
};
+#ifndef CONFIG_SYS_FLASH_CFI
/*
* I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
* Compass Sensor, Accelerometer, Res Touch
@@ -113,6 +118,7 @@ static struct i2c_pads_info i2c_pad_info2 = {
.gp = IMX_GPIO_NR(3, 18)
}
};
+#endif
static iomux_v3_cfg_t const i2c3_pads[] = {
MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
@@ -160,6 +166,75 @@ static int port_exp_direction_output(unsigned gpio, int value)
return 0;
}
+static iomux_v3_cfg_t const eimnor_pads[] = {
+ MX6_PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL) ,
+ MX6_PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void eimnor_cs_setup(void)
+{
+ struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
+
+ writel(0x00020181, &weim_regs->cs0gcr1);
+ writel(0x00000001, &weim_regs->cs0gcr2);
+ writel(0x0a020000, &weim_regs->cs0rcr1);
+ writel(0x0000c000, &weim_regs->cs0rcr2);
+ writel(0x0804a240, &weim_regs->cs0wcr1);
+ writel(0x00000120, &weim_regs->wcr);
+
+ set_chipselect_size(CS0_128);
+}
+
+static void setup_iomux_eimnor(void)
+{
+ imx_iomux_v3_setup_multiple_pads(eimnor_pads, ARRAY_SIZE(eimnor_pads));
+
+ gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
+
+ eimnor_cs_setup();
+}
+
static void setup_iomux_enet(void)
{
imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
@@ -402,6 +477,7 @@ int board_early_init_f(void)
#ifdef CONFIG_NAND_MXS
setup_gpmi_nand();
#endif
+
return 0;
}
@@ -415,11 +491,13 @@ int board_init(void)
/* I2C 3 Steer */
gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
+#ifndef CONFIG_SYS_FLASH_CFI
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
-
+#endif
gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp));
+ setup_iomux_eimnor();
return 0;
}
diff --git a/include/configs/mx6qsabreauto.h b/include/configs/mx6qsabreauto.h
index 3f1c88e..559937a 100644
--- a/include/configs/mx6qsabreauto.h
+++ b/include/configs/mx6qsabreauto.h
@@ -37,6 +37,16 @@
#include "mx6sabre_common.h"
+#undef CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR
+#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024)
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
+#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
#define CONFIG_SYS_FSL_USDHC_NUM 2
#if defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_SYS_MMC_ENV_DEV 0
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [U-Boot] [PATCH 1/3] imx: consolidate set_chipselect_size function
2014-11-14 13:27 [U-Boot] [PATCH 1/3] imx: consolidate set_chipselect_size function Fabio Estevam
2014-11-14 13:27 ` [U-Boot] [PATCH 2/3] mx6: add weim registers Fabio Estevam
2014-11-14 13:27 ` [U-Boot] [PATCH 3/3] mx6qsabreauto: Add parallel NOR flash support Fabio Estevam
@ 2014-11-20 9:38 ` Stefano Babic
2 siblings, 0 replies; 6+ messages in thread
From: Stefano Babic @ 2014-11-20 9:38 UTC (permalink / raw)
To: u-boot
On 14/11/2014 14:27, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam@freescale.com>
>
> Move MX5 specific set_chipselect_size function into generic i.MX part,
> such that MX6 based boards are able to use this function as well.
>
> While doing this the iomuxc gpr member needed to be consolidated between
> MX5 and MX6.
>
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> ---
> arch/arm/cpu/armv7/mx5/soc.c | 31 -------------------------------
> arch/arm/imx-common/cpu.c | 31 +++++++++++++++++++++++++++++++
> arch/arm/include/asm/arch-imx/cpu.h | 5 +++++
> arch/arm/include/asm/arch-mx5/imx-regs.h | 12 ++----------
> arch/arm/include/asm/arch-mx6/sys_proto.h | 1 +
> 5 files changed, 39 insertions(+), 41 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/mx5/soc.c b/arch/arm/cpu/armv7/mx5/soc.c
> index 2d53669..3753c14 100644
> --- a/arch/arm/cpu/armv7/mx5/soc.c
> +++ b/arch/arm/cpu/armv7/mx5/soc.c
> @@ -85,37 +85,6 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
> }
> #endif
>
> -void set_chipselect_size(int const cs_size)
> -{
> - unsigned int reg;
> - struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
> - reg = readl(&iomuxc_regs->gpr1);
> -
> - switch (cs_size) {
> - case CS0_128:
> - reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
> - reg |= 0x5;
> - break;
> - case CS0_64M_CS1_64M:
> - reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
> - reg |= 0x1B;
> - break;
> - case CS0_64M_CS1_32M_CS2_32M:
> - reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
> - reg |= 0x4B;
> - break;
> - case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
> - reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
> - reg |= 0x249;
> - break;
> - default:
> - printf("Unknown chip select size: %d\n", cs_size);
> - break;
> - }
> -
> - writel(reg, &iomuxc_regs->gpr1);
> -}
> -
> #ifdef CONFIG_MX53
> void boot_mode_apply(unsigned cfg_val)
> {
> diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
> index 09fc227..24740b8 100644
> --- a/arch/arm/imx-common/cpu.c
> +++ b/arch/arm/imx-common/cpu.c
> @@ -187,3 +187,34 @@ void arch_preboot_os(void)
> ipuv3_fb_shutdown();
> }
> #endif
> +
> +void set_chipselect_size(int const cs_size)
> +{
> + unsigned int reg;
> + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
> + reg = readl(&iomuxc_regs->gpr[1]);
> +
> + switch (cs_size) {
> + case CS0_128:
> + reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
> + reg |= 0x5;
> + break;
> + case CS0_64M_CS1_64M:
> + reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
> + reg |= 0x1B;
> + break;
> + case CS0_64M_CS1_32M_CS2_32M:
> + reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
> + reg |= 0x4B;
> + break;
> + case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
> + reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
> + reg |= 0x249;
> + break;
> + default:
> + printf("Unknown chip select size: %d\n", cs_size);
> + break;
> + }
> +
> + writel(reg, &iomuxc_regs->gpr[1]);
> +}
> diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
> index a3cc96f..254136e 100644
> --- a/arch/arm/include/asm/arch-imx/cpu.h
> +++ b/arch/arm/include/asm/arch-imx/cpu.h
> @@ -12,3 +12,8 @@
> #define MXC_CPU_MX6Q 0x63
> #define MXC_CPU_MX6D 0x64
> #define MXC_CPU_MX6SOLO 0x65 /* dummy ID */
> +
> +#define CS0_128 0
> +#define CS0_64M_CS1_64M 1
> +#define CS0_64M_CS1_32M_CS2_32M 2
> +#define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3
> diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
> index 054c680..f059d0f 100644
> --- a/arch/arm/include/asm/arch-mx5/imx-regs.h
> +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
> @@ -202,11 +202,6 @@
> */
> #define WBED 1
>
> -#define CS0_128 0
> -#define CS0_64M_CS1_64M 1
> -#define CS0_64M_CS1_32M_CS2_32M 2
> -#define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3
> -
> /*
> * CSPI register definitions
> */
> @@ -414,8 +409,7 @@ struct weim {
>
> #if defined(CONFIG_MX51)
> struct iomuxc {
> - u32 gpr0;
> - u32 gpr1;
> + u32 gpr[2];
> u32 omux0;
> u32 omux1;
> u32 omux2;
> @@ -424,9 +418,7 @@ struct iomuxc {
> };
> #elif defined(CONFIG_MX53)
> struct iomuxc {
> - u32 gpr0;
> - u32 gpr1;
> - u32 gpr2;
> + u32 gpr[3];
> u32 omux0;
> u32 omux1;
> u32 omux2;
> diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h
> index c35a905..28ba844 100644
> --- a/arch/arm/include/asm/arch-mx6/sys_proto.h
> +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
> @@ -26,6 +26,7 @@ u32 get_cpu_rev(void);
>
> const char *get_imx_type(u32 imxtype);
> unsigned imx_ddr_size(void);
> +void set_chipselect_size(int const);
>
> /*
> * Initializes on-chip ethernet controllers.
>
Applied to u-boot-imx, thanks !
Best regards,
Stefano Babic
--
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^ permalink raw reply [flat|nested] 6+ messages in thread