From mboxrd@z Thu Jan  1 00:00:00 1970
From: York Sun <yorksun@freescale.com>
Date: Tue, 25 Nov 2014 09:55:04 -0800
Subject: [U-Boot] [PATCH v2 2/5] arm: ls102xa: Remove bit reversing for
	SCFG registers
In-Reply-To: <1413530796-12881-2-git-send-email-b18965@freescale.com>
References: <1413530796-12881-1-git-send-email-b18965@freescale.com>
	<1413530796-12881-2-git-send-email-b18965@freescale.com>
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On 10/17/2014 12:26 AM, Alison Wang wrote:
> SCFG_SCFGREVCR is SCFG bit reverse register. This register
> must be written with 0xFFFFFFFF before writing to any other
> SCFG register. Then other SCFG register could be written in
> big-endian mode.
> 
> Address: 157_0000h base + 200h offset = 157_0200h
> Bit   0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15|16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
> W/R                                   SCFGREV
> Reset 0 0 0 0 0 0 0 0 0 0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
> 0-31
> SCFGREV SCFG Bit Reverse Control Filed
> 32'h 0000_0000 - No bit reverse is applied
> 32'h FFFF_FFFF - Bit reverse is applied; so 31:0 will be stored/read as
> 0:31
> 
> This patch removes the bit reversing for SCFG registers in
> u-boot. It will be implemented through PBI commands in RCW
> .pbi
> write 0x570200, 0xffffffff
> .end
> So other SCFG register could be written in big-endian mode
> in u-boot or kernel directly.
> 
> Signed-off-by: Alison Wang <alison.wang@freescale.com>
> ---
> Change log:
>  v2: Remove the defines for SCFG_SCFGREVCR_REV and
>      SCFG_SCFGREVCR_NOREV.
> 
>  arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 --
>  board/freescale/ls1021aqds/ls1021aqds.c           | 2 --
>  board/freescale/ls1021atwr/ls1021atwr.c           | 5 -----
>  3 files changed, 9 deletions(-)
> 

Applied to u-boot-fsl-qoriq master. Awaiting upstream. Thanks.

York