From mboxrd@z Thu Jan  1 00:00:00 1970
From: Stefan Roese <sr@denx.de>
Date: Mon, 08 Dec 2014 16:42:31 +0100
Subject: [U-Boot] [PATCH RFC] arm: mx6: Add CCGR0 configuration to
 default DCD (spl_sd.cfg)
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On 08.12.2014 16:36, Fabio Estevam wrote:
>>>> Could you test this on one of your board? If your board also fails to
>>>> boot
>>>> via the "bmode mmc0" command if the CCGR0 register value is missing?
>>>
>>>
>>> I am currently out of the office without access to my mx6 board,
>>
>>
>> I see. Perhaps you could do that once you are back in the office...
>
> Sure, I will test it and will let you know how it goes.

Thanks!

> In the meantime, I am wondering if the change below would allow your
> board to boot:
>
> --- a/arch/arm/cpu/armv7/mx6/soc.c
> +++ b/arch/arm/cpu/armv7/mx6/soc.c
> @@ -105,6 +105,10 @@ void init_aips(void)
>   #ifdef CONFIG_MX6SX
>          struct aipstz_regs *aips3;
>   #endif
> +       struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> +
> +       /* Turn on AIPS1 and AIPS2 clocks */
> +       setbits_le32(&ccm->CCGR0, 0xf);
>
>          aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
>          aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;

I just tested it. And it doesn't help. I really think this code is not 
reached in this failure case. As the SPL is not loaded completely.

Thanks,
Stefan