From mboxrd@z Thu Jan  1 00:00:00 1970
From: York Sun <yorksun@freescale.com>
Date: Tue, 16 Dec 2014 09:17:06 -0800
Subject: [U-Boot] [Patch v3] driver/ddr/fsl: Fix MRC_CYC calculation for
	DDR3
In-Reply-To: <1417547889-32435-1-git-send-email-yorksun@freescale.com>
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On 12/02/2014 11:18 AM, York Sun wrote:
> For DDR controller version 4.7 or newer, MRC_CYC (mode register set
> cycle time) is max(tMRD, tMOD). tMRD is 4nCK, or 8nCK (RDIMM). tMOD
> is max(12nCK, 15ns) according to JEDEC spec.
> 
> DDR4 is not affected by this change.
> 
> Signed-off-by: York Sun <yorksun@freescale.com>
> ---
> Change log
>  v3: Add cast for using max()
>  v2: Apply the change only to DDR controller newer than v4.7
>      Older DDRC needs to take into account of RDIMM for tMRD

Applied to u-boot-mpc85xx master, awaiting upstream.

York