From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jaehoon Chung Date: Tue, 23 Dec 2014 16:14:54 +0900 Subject: [U-Boot] [PATCH] arm: exynos: clock: support SPLL as mmc source clock for exynos5420 In-Reply-To: <1419245190-23604-1-git-send-email-jy0922.shim@samsung.com> References: <1419245190-23604-1-git-send-email-jy0922.shim@samsung.com> Message-ID: <5499166E.3010605@samsung.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Acked-by: Jaehoon Chung Best Regards, Jaehoon Chung On 12/22/2014 07:46 PM, Joonyoung Shim wrote: > MMC of exynos5420 can select SPLL as source clock, so add to support > SPLL in exynos5420_get_mmc_clk(). It was tested on Odroid-XU3 board. > > Signed-off-by: Joonyoung Shim > --- > arch/arm/cpu/armv7/exynos/clock.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c > index 8fab135..b31c13b 100644 > --- a/arch/arm/cpu/armv7/exynos/clock.c > +++ b/arch/arm/cpu/armv7/exynos/clock.c > @@ -848,6 +848,8 @@ static unsigned long exynos5420_get_mmc_clk(int dev_index) > > if (sel == 0x3) > sclk = get_pll_clk(MPLL); > + else if (sel == 0x4) > + sclk = get_pll_clk(SPLL); > else if (sel == 0x6) > sclk = get_pll_clk(EPLL); > else >