From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefan Roese Date: Tue, 06 Jan 2015 10:58:38 +0100 Subject: [U-Boot] [PATCH] spi: designware_spi: Fix detecting FIFO depth In-Reply-To: <1420502905.5011.1.camel@phoenix> References: <1420502905.5011.1.camel@phoenix> Message-ID: <54ABB1CE.4060402@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 06.01.2015 01:08, Axel Lin wrote: > Current code tries to find the highest valid fifo depth by checking the value > it wrote to DW_SPI_TXFLTR. There are a few problems in current code: > 1) There is an off-by-one in dws->fifo_len setting because it assumes the latest > register write fails so the latest valid value should be fifo - 1. > 2) We know the depth could be from 2 to 256 from HW spec, so it is not necessary > to test fifo == 257. In the case fifo is 257, it means the latest valid > setting is fifo = 256. So after the for loop iteration, we should check > fifo == 2 case instead of fifo == 257 if detecting the FIFO depth fails. > This patch fixes above issues. > > Signed-off-by: Axel Lin Acked-by: Stefan Roese Thanks, Stefan