[U-Boot] [PATCH 1/2] Errata/ARM57: Add basic constructs to handle and apply A57 specific erratas

[U-Boot] [PATCH 1/2] Errata/ARM57: Add basic constructs to handle and apply A57 specific erratas

[Bhupesh Sharma]

This patch adds basic constructs in the ARMv8 u-boot code
to handle and apply Cortex-A57 specific erratas.

As and example, the framework showcases how erratas 826974 and
828024 can be handled and applied.

Later on this framework can be extended to include other
erratas.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
---
 arch/arm/cpu/armv8/start.S   |   47 ++++++++++++++++++++++++++++++++++++++++++
 arch/arm/include/asm/macro.h |   20 ++++++++++++++++++
 2 files changed, 67 insertions(+)

diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 4b11aa4..d5bcf12 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -100,6 +100,8 @@ master_cpu:
 WEAK(lowlevel_init)
 	mov	x29, lr			/* Save LR */
 
+	bl	apply_core_errata
+
 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
 	branch_if_slave x0, 1f
 	ldr	x0, =GICD_BASE
@@ -155,6 +157,51 @@ ENDPROC(smp_kick_all_cpus)
 
 /*-----------------------------------------------------------------------*/
 
+WEAK(apply_core_errata)
+	mov	x29, lr			/* Save LR */
+
+	/* For now, we support Cortex-A57 specific errata only */
+
+	/* Check if we are running on a Cortex-A57 core */
+	branch_if_a57_core x0, 1f
+	b	2f
+1:
+	bl	apply_a57_core_errata
+
+2:
+	mov	lr, x29			/* Restore LR */
+	ret
+ENDPROC(apply_core_errata)
+
+/*-----------------------------------------------------------------------*/
+
+WEAK(apply_a57_core_errata)
+	mov	x29, lr			/* Save LR */
+
+#ifdef CONFIG_ARM_ERRATA_828024
+	mrs	x0, S3_1_c15_c2_0	/* cpuactlr_el1 */
+	/* Disable non-allocate hint of w-b-n-a memory type */
+	mov	x0, #0x1 << 49
+	/* Disable write streaming no L1-allocate threshold */
+	mov	x0, #0x3 << 25
+	/* Disable write streaming no-allocate threshold */
+	mov	x0, #0x3 << 27
+	msr	S3_1_c15_c2_0, x0	/* cpuactlr_el1 */
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_826974
+	mrs	x0, S3_1_c15_c2_0	/* cpuactlr_el1 */
+	/* Disable speculative load execution ahead of a DMB */
+	mov	x0, #0x1 << 59
+	msr	S3_1_c15_c2_0, x0	/* cpuactlr_el1 */
+#endif
+
+	mov	lr, x29			/* Restore LR */
+	ret
+ENDPROC(apply_a57_core_errata)
+
+/*-----------------------------------------------------------------------*/
+
 ENTRY(c_runtime_cpu_setup)
 	/* Relocate vBAR */
 	adr	x0, vectors
diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h
index 1c8c425..13bae37 100644
--- a/arch/arm/include/asm/macro.h
+++ b/arch/arm/include/asm/macro.h
@@ -74,6 +74,26 @@ lr	.req	x30
 .endm
 
 /*
+ * Branch if current processor is a Cortex-A57 core.
+ */
+.macro	branch_if_a57_core, xreg, a57_label
+	mrs	\xreg, midr_el1
+	lsr	\xreg, \xreg, #4
+	cmp	\xreg, #0xD07		/* Cortex-A57 MPCore processor. */
+	b.eq	\a57_label
+.endm
+
+/*
+ * Branch if current processor is a Cortex-A53 core.
+ */
+.macro	branch_if_a53_core, xreg, a53_label
+	mrs	\xreg, midr_el1
+	lsr	\xreg, \xreg, #4
+	cmp	\xreg, #0xD03		/* Cortex-A53 MPCore processor. */
+	b.eq	\a53_label
+.endm
+
+/*
  * Branch if current processor is a slave,
  * choose processor with all zero affinity value as the master.
  */
-- 
1.7.9.5

[U-Boot] [PATCH 2/2] configs/ls2085a: Add support for Cortex-A57 erratas

[Bhupesh Sharma]

This patch adds support for handling 828024 and 826974 erratas
for Cortex-A57 cores present on LS2085A SoC.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
---
 include/configs/ls2085a_common.h |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h
index 6fe032c..01c8566 100644
--- a/include/configs/ls2085a_common.h
+++ b/include/configs/ls2085a_common.h
@@ -14,6 +14,10 @@
 #define CONFIG_LS2085A
 #define CONFIG_GICV3
 
+/* Errata fixes */
+#define CONFIG_ARM_ERRATA_828024
+#define CONFIG_ARM_ERRATA_826974
+
 /* Link Definitions */
 #define CONFIG_SYS_TEXT_BASE		0x30001000
 
-- 
1.7.9.5

[U-Boot] [PATCH 1/2] Errata/ARM57: Add basic constructs to handle and apply A57 specific erratas

[York Sun]

On 01/13/2015 05:19 AM, Bhupesh Sharma wrote:
> This patch adds basic constructs in the ARMv8 u-boot code
> to handle and apply Cortex-A57 specific erratas.
> 
> As and example, the framework showcases how erratas 826974 and
> 828024 can be handled and applied.
> 
> Later on this framework can be extended to include other
> erratas.
> 
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
> ---
>  arch/arm/cpu/armv8/start.S   |   47 ++++++++++++++++++++++++++++++++++++++++++
>  arch/arm/include/asm/macro.h |   20 ++++++++++++++++++
>  2 files changed, 67 insertions(+)
> 
> diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
> index 4b11aa4..d5bcf12 100644
> --- a/arch/arm/cpu/armv8/start.S
> +++ b/arch/arm/cpu/armv8/start.S
> @@ -100,6 +100,8 @@ master_cpu:
>  WEAK(lowlevel_init)
>  	mov	x29, lr			/* Save LR */
>  
> +	bl	apply_core_errata
> +
>  #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
>  	branch_if_slave x0, 1f
>  	ldr	x0, =GICD_BASE
> @@ -155,6 +157,51 @@ ENDPROC(smp_kick_all_cpus)
>  
>  /*-----------------------------------------------------------------------*/
>  
> +WEAK(apply_core_errata)
> +	mov	x29, lr			/* Save LR */
> +
> +	/* For now, we support Cortex-A57 specific errata only */
> +
> +	/* Check if we are running on a Cortex-A57 core */
> +	branch_if_a57_core x0, 1f
> +	b	2f
> +1:
> +	bl	apply_a57_core_errata
> +
> +2:
> +	mov	lr, x29			/* Restore LR */
> +	ret
> +ENDPROC(apply_core_errata)
> +
> +/*-----------------------------------------------------------------------*/
> +
> +WEAK(apply_a57_core_errata)
> +	mov	x29, lr			/* Save LR */
> +
> +#ifdef CONFIG_ARM_ERRATA_828024
> +	mrs	x0, S3_1_c15_c2_0	/* cpuactlr_el1 */
> +	/* Disable non-allocate hint of w-b-n-a memory type */
> +	mov	x0, #0x1 << 49
> +	/* Disable write streaming no L1-allocate threshold */
> +	mov	x0, #0x3 << 25
> +	/* Disable write streaming no-allocate threshold */
> +	mov	x0, #0x3 << 27
> +	msr	S3_1_c15_c2_0, x0	/* cpuactlr_el1 */
> +#endif
> +
> +#ifdef CONFIG_ARM_ERRATA_826974
> +	mrs	x0, S3_1_c15_c2_0	/* cpuactlr_el1 */
> +	/* Disable speculative load execution ahead of a DMB */
> +	mov	x0, #0x1 << 59
> +	msr	S3_1_c15_c2_0, x0	/* cpuactlr_el1 */
> +#endif
> +
> +	mov	lr, x29			/* Restore LR */
> +	ret
> +ENDPROC(apply_a57_core_errata)
> +

Bhupesh,

Have you tested your patch on simulator/emulator? It seems you use x29
recursively. x29 holds the return address for function lowlevel_init. You use it
multiple times, so the program will not run correctly.

Beside, you implement this framework in lowlevel_init function, which is a weak
function. I guess you may have tested for LS2085A simulator, but we have a
different lowlevel_init function implemented. You may want to add a new function
call before "bl lowlevel_init".

York

[U-Boot] [PATCH 1/2] Errata/ARM57: Add basic constructs to handle and apply A57 specific erratas

[bhupesh.sharma at freescale.com]

Hi York,

> -----Original Message-----
> From: Sun York-R58495
> Sent: Tuesday, January 13, 2015 10:01 PM

> On 01/13/2015 05:19 AM, Bhupesh Sharma wrote:
> > This patch adds basic constructs in the ARMv8 u-boot code to handle
> > and apply Cortex-A57 specific erratas.
> >
> > As and example, the framework showcases how erratas 826974 and
> > 828024 can be handled and applied.
> >
> > Later on this framework can be extended to include other erratas.
> >
> > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
> > ---
> >  arch/arm/cpu/armv8/start.S   |   47
> ++++++++++++++++++++++++++++++++++++++++++
> >  arch/arm/include/asm/macro.h |   20 ++++++++++++++++++
> >  2 files changed, 67 insertions(+)
> >
> > diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
> > index 4b11aa4..d5bcf12 100644
> > --- a/arch/arm/cpu/armv8/start.S
> > +++ b/arch/arm/cpu/armv8/start.S
> > @@ -100,6 +100,8 @@ master_cpu:
> >  WEAK(lowlevel_init)
> >  	mov	x29, lr			/* Save LR */
> >
> > +	bl	apply_core_errata
> > +
> >  #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
> >  	branch_if_slave x0, 1f
> >  	ldr	x0, =GICD_BASE
> > @@ -155,6 +157,51 @@ ENDPROC(smp_kick_all_cpus)
> >
> >
> > /*--------------------------------------------------------------------
> > ---*/
> >
> > +WEAK(apply_core_errata)
> > +	mov	x29, lr			/* Save LR */
> > +
> > +	/* For now, we support Cortex-A57 specific errata only */
> > +
> > +	/* Check if we are running on a Cortex-A57 core */
> > +	branch_if_a57_core x0, 1f
> > +	b	2f
> > +1:
> > +	bl	apply_a57_core_errata
> > +
> > +2:
> > +	mov	lr, x29			/* Restore LR */
> > +	ret
> > +ENDPROC(apply_core_errata)
> > +
> > +/*-------------------------------------------------------------------
> > +----*/
> > +
> > +WEAK(apply_a57_core_errata)
> > +	mov	x29, lr			/* Save LR */
> > +
> > +#ifdef CONFIG_ARM_ERRATA_828024
> > +	mrs	x0, S3_1_c15_c2_0	/* cpuactlr_el1 */
> > +	/* Disable non-allocate hint of w-b-n-a memory type */
> > +	mov	x0, #0x1 << 49
> > +	/* Disable write streaming no L1-allocate threshold */
> > +	mov	x0, #0x3 << 25
> > +	/* Disable write streaming no-allocate threshold */
> > +	mov	x0, #0x3 << 27
> > +	msr	S3_1_c15_c2_0, x0	/* cpuactlr_el1 */
> > +#endif
> > +
> > +#ifdef CONFIG_ARM_ERRATA_826974
> > +	mrs	x0, S3_1_c15_c2_0	/* cpuactlr_el1 */
> > +	/* Disable speculative load execution ahead of a DMB */
> > +	mov	x0, #0x1 << 59
> > +	msr	S3_1_c15_c2_0, x0	/* cpuactlr_el1 */
> > +#endif
> > +
> > +	mov	lr, x29			/* Restore LR */
> > +	ret
> > +ENDPROC(apply_a57_core_errata)
> > +
> 
> Bhupesh,
> 
> Have you tested your patch on simulator/emulator? It seems you use x29
> recursively. x29 holds the return address for function lowlevel_init. You
> use it multiple times, so the program will not run correctly.
> 
> Beside, you implement this framework in lowlevel_init function, which is
> a weak function. I guess you may have tested for LS2085A simulator, but
> we have a different lowlevel_init function implemented. You may want to
> add a new function call before "bl lowlevel_init".
> 

Thanks for catching this. Seems like I unintentionally sent out the wrong version of
the patches. I will send the correct set of patches soon.

Regards,
Bhupesh