[U-Boot] [PATCH v2 1/2] Errata/ARM57: Add basic constructs to handle and apply A57 specific erratas

[U-Boot] [PATCH v2 1/2] Errata/ARM57: Add basic constructs to handle and apply A57 specific erratas

[Bhupesh Sharma]

This patch adds basic constructs in the ARMv8 u-boot code
to handle and apply Cortex-A57 specific erratas.

As and example, the framework showcases how erratas 833069, 826974
and 828024 can be handled and applied.

Later on this framework can be extended to include other
erratas.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
---
Changes from v1:
	- Addressed York's comment about x29 usage and calling the
	  core errata fxup function before the lowlevel_init function
	  is called.

 arch/arm/cpu/armv8/start.S   |   51 ++++++++++++++++++++++++++++++++++++++++++
 arch/arm/include/asm/macro.h |   20 +++++++++++++++++
 2 files changed, 71 insertions(+)

diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 4b11aa4..df532f9 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -67,6 +67,9 @@ reset:
 	msr	cpacr_el1, x0			/* Enable FP/SIMD */
 0:
 
+	/* Apply ARM core specific erratas */
+	bl	apply_core_errata
+
 	/*
 	 * Cache/BPB/TLB Invalidate
 	 * i-cache is invalidated before enabled in icache_enable()
@@ -97,6 +100,54 @@ master_cpu:
 
 /*-----------------------------------------------------------------------*/
 
+WEAK(apply_core_errata)
+
+	/* For now, we support Cortex-A57 specific errata only */
+
+	/* Check if we are running on a Cortex-A57 core */
+	branch_if_a57_core x0, 1f
+	b	2f
+1:
+	bl	apply_a57_core_errata
+
+2:
+	ret
+ENDPROC(apply_core_errata)
+
+/*-----------------------------------------------------------------------*/
+
+WEAK(apply_a57_core_errata)
+
+#ifdef CONFIG_ARM_ERRATA_828024
+	mrs	x0, S3_1_c15_c2_0	/* cpuactlr_el1 */
+	/* Disable non-allocate hint of w-b-n-a memory type */
+	mov	x0, #0x1 << 49
+	/* Disable write streaming no L1-allocate threshold */
+	mov	x0, #0x3 << 25
+	/* Disable write streaming no-allocate threshold */
+	mov	x0, #0x3 << 27
+	msr	S3_1_c15_c2_0, x0	/* cpuactlr_el1 */
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_826974
+	mrs	x0, S3_1_c15_c2_0	/* cpuactlr_el1 */
+	/* Disable speculative load execution ahead of a DMB */
+	mov	x0, #0x1 << 59
+	msr	S3_1_c15_c2_0, x0	/* cpuactlr_el1 */
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_833069
+	mrs	x0, S3_1_c15_c2_0	/* cpuactlr_el1 */
+	/* Disable Enable Invalidates of BTB bit */
+	and	x0, x0, #0xE
+	msr	S3_1_c15_c2_0, x0	/* cpuactlr_el1 */
+#endif
+
+	ret
+ENDPROC(apply_a57_core_errata)
+
+/*-----------------------------------------------------------------------*/
+
 WEAK(lowlevel_init)
 	mov	x29, lr			/* Save LR */
 
diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h
index 1c8c425..13bae37 100644
--- a/arch/arm/include/asm/macro.h
+++ b/arch/arm/include/asm/macro.h
@@ -74,6 +74,26 @@ lr	.req	x30
 .endm
 
 /*
+ * Branch if current processor is a Cortex-A57 core.
+ */
+.macro	branch_if_a57_core, xreg, a57_label
+	mrs	\xreg, midr_el1
+	lsr	\xreg, \xreg, #4
+	cmp	\xreg, #0xD07		/* Cortex-A57 MPCore processor. */
+	b.eq	\a57_label
+.endm
+
+/*
+ * Branch if current processor is a Cortex-A53 core.
+ */
+.macro	branch_if_a53_core, xreg, a53_label
+	mrs	\xreg, midr_el1
+	lsr	\xreg, \xreg, #4
+	cmp	\xreg, #0xD03		/* Cortex-A53 MPCore processor. */
+	b.eq	\a53_label
+.endm
+
+/*
  * Branch if current processor is a slave,
  * choose processor with all zero affinity value as the master.
  */
-- 
1.7.9.5

[U-Boot] [PATCH v2 2/2] configs/ls2085a: Add support for Cortex-A57 erratas

[Bhupesh Sharma]

This patch adds support for handling 828024 and 826974 erratas
for Cortex-A57 cores present on LS2085A SoC.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
---
 include/configs/ls2085a_common.h |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h
index 6fe032c..01c8566 100644
--- a/include/configs/ls2085a_common.h
+++ b/include/configs/ls2085a_common.h
@@ -14,6 +14,10 @@
 #define CONFIG_LS2085A
 #define CONFIG_GICV3
 
+/* Errata fixes */
+#define CONFIG_ARM_ERRATA_828024
+#define CONFIG_ARM_ERRATA_826974
+
 /* Link Definitions */
 #define CONFIG_SYS_TEXT_BASE		0x30001000
 
-- 
1.7.9.5

[U-Boot] [PATCH v2 1/2] Errata/ARM57: Add basic constructs to handle and apply A57 specific erratas

[York Sun]

On 01/14/2015 05:46 AM, Bhupesh Sharma wrote:
> This patch adds basic constructs in the ARMv8 u-boot code
> to handle and apply Cortex-A57 specific erratas.
> 
> As and example, the framework showcases how erratas 833069, 826974
> and 828024 can be handled and applied.
> 
> Later on this framework can be extended to include other
> erratas.
> 
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
> ---
> Changes from v1:
> 	- Addressed York's comment about x29 usage and calling the
> 	  core errata fxup function before the lowlevel_init function
> 	  is called.
> 
>  arch/arm/cpu/armv8/start.S   |   51 ++++++++++++++++++++++++++++++++++++++++++
>  arch/arm/include/asm/macro.h |   20 +++++++++++++++++
>  2 files changed, 71 insertions(+)
> 
> diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
> index 4b11aa4..df532f9 100644
> --- a/arch/arm/cpu/armv8/start.S
> +++ b/arch/arm/cpu/armv8/start.S
> @@ -67,6 +67,9 @@ reset:
>  	msr	cpacr_el1, x0			/* Enable FP/SIMD */
>  0:
>  
> +	/* Apply ARM core specific erratas */
> +	bl	apply_core_errata
> +
>  	/*
>  	 * Cache/BPB/TLB Invalidate
>  	 * i-cache is invalidated before enabled in icache_enable()
> @@ -97,6 +100,54 @@ master_cpu:
>  
>  /*-----------------------------------------------------------------------*/
>  
> +WEAK(apply_core_errata)
> +
> +	/* For now, we support Cortex-A57 specific errata only */
> +
> +	/* Check if we are running on a Cortex-A57 core */
> +	branch_if_a57_core x0, 1f
> +	b	2f
> +1:
> +	bl	apply_a57_core_errata
> +
> +2:
> +	ret
> +ENDPROC(apply_core_errata)
> +

Bhupesh,

Have you tested the new code? I don't think it handles LR correctly. Your code
will be stuck.

York

[U-Boot] [PATCH v2 1/2] Errata/ARM57: Add basic constructs to handle and apply A57 specific erratas

[bhupesh.sharma at freescale.com]

Hi York,

> -----Original Message-----
> From: Sun York-R58495
> Sent: Wednesday, January 14, 2015 9:44 PM
> On 01/14/2015 05:46 AM, Bhupesh Sharma wrote:
> > This patch adds basic constructs in the ARMv8 u-boot code to handle
> > and apply Cortex-A57 specific erratas.
> >
> > As and example, the framework showcases how erratas 833069, 826974 and
> > 828024 can be handled and applied.
> >
> > Later on this framework can be extended to include other erratas.
> >
> > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
> > ---
> > Changes from v1:
> > 	- Addressed York's comment about x29 usage and calling the
> > 	  core errata fxup function before the lowlevel_init function
> > 	  is called.
> >
> >  arch/arm/cpu/armv8/start.S   |   51
> ++++++++++++++++++++++++++++++++++++++++++
> >  arch/arm/include/asm/macro.h |   20 +++++++++++++++++
> >  2 files changed, 71 insertions(+)
> >
> > diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
> > index 4b11aa4..df532f9 100644
> > --- a/arch/arm/cpu/armv8/start.S
> > +++ b/arch/arm/cpu/armv8/start.S
> > @@ -67,6 +67,9 @@ reset:
> >  	msr	cpacr_el1, x0			/* Enable FP/SIMD */
> >  0:
> >
> > +	/* Apply ARM core specific erratas */
> > +	bl	apply_core_errata
> > +
> >  	/*
> >  	 * Cache/BPB/TLB Invalidate
> >  	 * i-cache is invalidated before enabled in icache_enable() @@ -
> 97,6
> > +100,54 @@ master_cpu:
> >
> >
> > /*--------------------------------------------------------------------
> > ---*/
> >
> > +WEAK(apply_core_errata)
> > +
> > +	/* For now, we support Cortex-A57 specific errata only */
> > +
> > +	/* Check if we are running on a Cortex-A57 core */
> > +	branch_if_a57_core x0, 1f
> > +	b	2f
> > +1:
> > +	bl	apply_a57_core_errata
> > +
> > +2:
> > +	ret
> > +ENDPROC(apply_core_errata)
> > +
> 
> Bhupesh,
> 
> Have you tested the new code? I don't think it handles LR correctly. Your
> code will be stuck.
> 

Yes, I have tested this on both the LS2085A simulator and emulator platforms.
On emulator I tried u-boot boot-to-prompt and on simulator I tried linux boot-to-prompt.
Both seem to be working fine.

Regards,
Bhupesh

[U-Boot] [PATCH v2 1/2] Errata/ARM57: Add basic constructs to handle and apply A57 specific erratas

[Mark Rutland]

On Thu, Jan 15, 2015 at 06:10:57AM +0000, bhupesh.sharma at freescale.com wrote:
> Hi York,
> 
> > -----Original Message-----
> > From: Sun York-R58495
> > Sent: Wednesday, January 14, 2015 9:44 PM
> > On 01/14/2015 05:46 AM, Bhupesh Sharma wrote:
> > > This patch adds basic constructs in the ARMv8 u-boot code to handle
> > > and apply Cortex-A57 specific erratas.
> > >
> > > As and example, the framework showcases how erratas 833069, 826974 and
> > > 828024 can be handled and applied.
> > >
> > > Later on this framework can be extended to include other erratas.
> > >
> > > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
> > > ---
> > > Changes from v1:
> > > 	- Addressed York's comment about x29 usage and calling the
> > > 	  core errata fxup function before the lowlevel_init function
> > > 	  is called.
> > >
> > >  arch/arm/cpu/armv8/start.S   |   51
> > ++++++++++++++++++++++++++++++++++++++++++
> > >  arch/arm/include/asm/macro.h |   20 +++++++++++++++++
> > >  2 files changed, 71 insertions(+)
> > >
> > > diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
> > > index 4b11aa4..df532f9 100644
> > > --- a/arch/arm/cpu/armv8/start.S
> > > +++ b/arch/arm/cpu/armv8/start.S
> > > @@ -67,6 +67,9 @@ reset:
> > >  	msr	cpacr_el1, x0			/* Enable FP/SIMD */
> > >  0:
> > >
> > > +	/* Apply ARM core specific erratas */
> > > +	bl	apply_core_errata
> > > +
> > >  	/*
> > >  	 * Cache/BPB/TLB Invalidate
> > >  	 * i-cache is invalidated before enabled in icache_enable() @@ -
> > 97,6
> > > +100,54 @@ master_cpu:
> > >
> > >
> > > /*--------------------------------------------------------------------
> > > ---*/
> > >
> > > +WEAK(apply_core_errata)
> > > +
> > > +	/* For now, we support Cortex-A57 specific errata only */
> > > +
> > > +	/* Check if we are running on a Cortex-A57 core */
> > > +	branch_if_a57_core x0, 1f
> > > +	b	2f
> > > +1:
> > > +	bl	apply_a57_core_errata
> > > +
> > > +2:
> > > +	ret
> > > +ENDPROC(apply_core_errata)
> > > +
> > 
> > Bhupesh,
> > 
> > Have you tested the new code? I don't think it handles LR correctly. Your
> > code will be stuck.
> > 
> 
> Yes, I have tested this on both the LS2085A simulator and emulator platforms.
> On emulator I tried u-boot boot-to-prompt and on simulator I tried linux boot-to-prompt.
> Both seem to be working fine.

Has the apply_a57_core_errata function definitely been called in your
tests?

If so the lr should point immediately after it (i.e. at the ret), and so
the ret should branch to itself, repeatedly.

Mark.

[U-Boot] [PATCH v2 1/2] Errata/ARM57: Add basic constructs to handle and apply A57 specific erratas

[bhupesh.sharma at freescale.com]

Hi Mark,

> -----Original Message-----
> From: Mark Rutland [mailto:mark.rutland at arm.com]
> Sent: Friday, January 16, 2015 12:35 AM
> To: Sharma Bhupesh-B45370
> Cc: Sun York-R58495; u-boot at lists.denx.de; albert.u.boot at aribaud.net;
> Wood Scott-B07421; Yoder Stuart-B08248
> Subject: Re: [U-Boot] [PATCH v2 1/2] Errata/ARM57: Add basic constructs
> to handle and apply A57 specific erratas
> 
> On Thu, Jan 15, 2015 at 06:10:57AM +0000, bhupesh.sharma at freescale.com
> wrote:
> > Hi York,
> >
> > > -----Original Message-----
> > > From: Sun York-R58495
> > > Sent: Wednesday, January 14, 2015 9:44 PM On 01/14/2015 05:46 AM,
> > > Bhupesh Sharma wrote:
> > > > This patch adds basic constructs in the ARMv8 u-boot code to
> > > > handle and apply Cortex-A57 specific erratas.
> > > >
> > > > As and example, the framework showcases how erratas 833069, 826974
> > > > and
> > > > 828024 can be handled and applied.
> > > >
> > > > Later on this framework can be extended to include other erratas.
> > > >
> > > > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
> > > > ---
> > > > Changes from v1:
> > > > 	- Addressed York's comment about x29 usage and calling the
> > > > 	  core errata fxup function before the lowlevel_init function
> > > > 	  is called.
> > > >
> > > >  arch/arm/cpu/armv8/start.S   |   51
> > > ++++++++++++++++++++++++++++++++++++++++++
> > > >  arch/arm/include/asm/macro.h |   20 +++++++++++++++++
> > > >  2 files changed, 71 insertions(+)
> > > >
> > > > diff --git a/arch/arm/cpu/armv8/start.S
> > > > b/arch/arm/cpu/armv8/start.S index 4b11aa4..df532f9 100644
> > > > --- a/arch/arm/cpu/armv8/start.S
> > > > +++ b/arch/arm/cpu/armv8/start.S
> > > > @@ -67,6 +67,9 @@ reset:
> > > >  	msr	cpacr_el1, x0			/* Enable FP/SIMD */
> > > >  0:
> > > >
> > > > +	/* Apply ARM core specific erratas */
> > > > +	bl	apply_core_errata
> > > > +
> > > >  	/*
> > > >  	 * Cache/BPB/TLB Invalidate
> > > >  	 * i-cache is invalidated before enabled in icache_enable()
> @@ -
> > > 97,6
> > > > +100,54 @@ master_cpu:
> > > >
> > > >
> > > > /*----------------------------------------------------------------
> > > > ----
> > > > ---*/
> > > >
> > > > +WEAK(apply_core_errata)
> > > > +
> > > > +	/* For now, we support Cortex-A57 specific errata only */
> > > > +
> > > > +	/* Check if we are running on a Cortex-A57 core */
> > > > +	branch_if_a57_core x0, 1f
> > > > +	b	2f
> > > > +1:
> > > > +	bl	apply_a57_core_errata
> > > > +
> > > > +2:
> > > > +	ret
> > > > +ENDPROC(apply_core_errata)
> > > > +
> > >
> > > Bhupesh,
> > >
> > > Have you tested the new code? I don't think it handles LR correctly.
> > > Your code will be stuck.
> > >
> >
> > Yes, I have tested this on both the LS2085A simulator and emulator
> platforms.
> > On emulator I tried u-boot boot-to-prompt and on simulator I tried
> linux boot-to-prompt.
> > Both seem to be working fine.
> 
> Has the apply_a57_core_errata function definitely been called in your
> tests?
> 
> If so the lr should point immediately after it (i.e. at the ret), and so
> the ret should branch to itself, repeatedly.
> 

Thanks for the pointers. Let me connect a debugger and see the step-by-step flow
through the apply_a57_core_errata.

I will revert with the findings soon.

Regards,
Bhupesh

[U-Boot] [PATCH v2 1/2] Errata/ARM57: Add basic constructs to handle and apply A57 specific erratas

[York Sun]

On 01/15/2015 11:05 AM, Mark Rutland wrote:
> On Thu, Jan 15, 2015 at 06:10:57AM +0000, bhupesh.sharma at freescale.com wrote:
>> Hi York,
>>
>>> -----Original Message-----
>>> From: Sun York-R58495
>>> Sent: Wednesday, January 14, 2015 9:44 PM
>>> On 01/14/2015 05:46 AM, Bhupesh Sharma wrote:
>>>> This patch adds basic constructs in the ARMv8 u-boot code to handle
>>>> and apply Cortex-A57 specific erratas.
>>>>
>>>> As and example, the framework showcases how erratas 833069, 826974 and
>>>> 828024 can be handled and applied.
>>>>
>>>> Later on this framework can be extended to include other erratas.
>>>>
>>>> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
>>>> ---
>>>> Changes from v1:
>>>> 	- Addressed York's comment about x29 usage and calling the
>>>> 	  core errata fxup function before the lowlevel_init function
>>>> 	  is called.
>>>>
>>>>  arch/arm/cpu/armv8/start.S   |   51
>>> ++++++++++++++++++++++++++++++++++++++++++
>>>>  arch/arm/include/asm/macro.h |   20 +++++++++++++++++
>>>>  2 files changed, 71 insertions(+)
>>>>
>>>> diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
>>>> index 4b11aa4..df532f9 100644
>>>> --- a/arch/arm/cpu/armv8/start.S
>>>> +++ b/arch/arm/cpu/armv8/start.S
>>>> @@ -67,6 +67,9 @@ reset:
>>>>  	msr	cpacr_el1, x0			/* Enable FP/SIMD */
>>>>  0:
>>>>
>>>> +	/* Apply ARM core specific erratas */
>>>> +	bl	apply_core_errata
>>>> +
>>>>  	/*
>>>>  	 * Cache/BPB/TLB Invalidate
>>>>  	 * i-cache is invalidated before enabled in icache_enable() @@ -
>>> 97,6
>>>> +100,54 @@ master_cpu:
>>>>
>>>>
>>>> /*--------------------------------------------------------------------
>>>> ---*/
>>>>
>>>> +WEAK(apply_core_errata)
>>>> +
>>>> +	/* For now, we support Cortex-A57 specific errata only */
>>>> +
>>>> +	/* Check if we are running on a Cortex-A57 core */
>>>> +	branch_if_a57_core x0, 1f
>>>> +	b	2f
>>>> +1:
>>>> +	bl	apply_a57_core_errata
>>>> +
>>>> +2:
>>>> +	ret
>>>> +ENDPROC(apply_core_errata)
>>>> +
>>>
>>> Bhupesh,
>>>
>>> Have you tested the new code? I don't think it handles LR correctly. Your
>>> code will be stuck.
>>>
>>
>> Yes, I have tested this on both the LS2085A simulator and emulator platforms.
>> On emulator I tried u-boot boot-to-prompt and on simulator I tried linux boot-to-prompt.
>> Both seem to be working fine.
> 
> Has the apply_a57_core_errata function definitely been called in your
> tests?
> 
> If so the lr should point immediately after it (i.e. at the ret), and so
> the ret should branch to itself, repeatedly.
> 

That's what I thought. I wonder how Bhupesh tested on the simulator.

York

[U-Boot] [PATCH v2 1/2] Errata/ARM57: Add basic constructs to handle and apply A57 specific erratas

[Scott Wood]

On Wed, 2015-01-14 at 19:16 +0530, Bhupesh Sharma wrote:
> This patch adds basic constructs in the ARMv8 u-boot code
> to handle and apply Cortex-A57 specific erratas.
> 
> As and example, the framework showcases how erratas 833069, 826974
> and 828024 can be handled and applied.
> 
> Later on this framework can be extended to include other
> erratas.
> 
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
> ---
> Changes from v1:
> 	- Addressed York's comment about x29 usage and calling the
> 	  core errata fxup function before the lowlevel_init function
> 	  is called.
> 
>  arch/arm/cpu/armv8/start.S   |   51 ++++++++++++++++++++++++++++++++++++++++++
>  arch/arm/include/asm/macro.h |   20 +++++++++++++++++
>  2 files changed, 71 insertions(+)
> 
> diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
> index 4b11aa4..df532f9 100644
> --- a/arch/arm/cpu/armv8/start.S
> +++ b/arch/arm/cpu/armv8/start.S
> @@ -67,6 +67,9 @@ reset:
>  	msr	cpacr_el1, x0			/* Enable FP/SIMD */
>  0:
>  
> +	/* Apply ARM core specific erratas */
> +	bl	apply_core_errata
> +
>  	/*
>  	 * Cache/BPB/TLB Invalidate
>  	 * i-cache is invalidated before enabled in icache_enable()
> @@ -97,6 +100,54 @@ master_cpu:
>  
>  /*-----------------------------------------------------------------------*/
>  
> +WEAK(apply_core_errata)
> +
> +	/* For now, we support Cortex-A57 specific errata only */
> +
> +	/* Check if we are running on a Cortex-A57 core */
> +	branch_if_a57_core x0, 1f
> +	b	2f
> +1:
> +	bl	apply_a57_core_errata
> +
> +2:

This is awkward.  How often are you expecting to use this macro?  Why
not just open-code it?  Or at least make it "branch_if_not_a57_core".
Or fix your lr problem by doing "branch_if_a57_core
apply_a57_core_errata" and having it branch back rather than "ret".

But I think opencoding would be best.  Just define symbols for the
actual core IDs.

> +WEAK(apply_a57_core_errata)

Why is this weak?

-Scott

[U-Boot] [PATCH v2 1/2] Errata/ARM57: Add basic constructs to handle and apply A57 specific erratas

[Arnab Basu]

On Fri, Jan 16, 2015 at 2:10 AM, Scott Wood <scottwood@freescale.com> wrote:

> On Wed, 2015-01-14 at 19:16 +0530, Bhupesh Sharma wrote:
> > This patch adds basic constructs in the ARMv8 u-boot code
> > to handle and apply Cortex-A57 specific erratas.
> >
> > As and example, the framework showcases how erratas 833069, 826974
> > and 828024 can be handled and applied.
> >
> > Later on this framework can be extended to include other
> > erratas.
> >
> > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
> > ---
> > Changes from v1:
> >       - Addressed York's comment about x29 usage and calling the
> >         core errata fxup function before the lowlevel_init function
> >         is called.
> >
> >  arch/arm/cpu/armv8/start.S   |   51
> ++++++++++++++++++++++++++++++++++++++++++
> >  arch/arm/include/asm/macro.h |   20 +++++++++++++++++
> >  2 files changed, 71 insertions(+)
> >
> > diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
> > index 4b11aa4..df532f9 100644
> > --- a/arch/arm/cpu/armv8/start.S
> > +++ b/arch/arm/cpu/armv8/start.S
> > @@ -67,6 +67,9 @@ reset:
> >       msr     cpacr_el1, x0                   /* Enable FP/SIMD */
> >  0:
> >
> > +     /* Apply ARM core specific erratas */
> > +     bl      apply_core_errata
> > +
> >       /*
> >        * Cache/BPB/TLB Invalidate
> >        * i-cache is invalidated before enabled in icache_enable()
> > @@ -97,6 +100,54 @@ master_cpu:
> >
> >
> /*-----------------------------------------------------------------------*/
> >
> > +WEAK(apply_core_errata)
> > +
> > +     /* For now, we support Cortex-A57 specific errata only */
> > +
> > +     /* Check if we are running on a Cortex-A57 core */
> > +     branch_if_a57_core x0, 1f
> > +     b       2f
> > +1:
> > +     bl      apply_a57_core_errata
> > +
> > +2:
>
> This is awkward.  How often are you expecting to use this macro?  Why
> not just open-code it?  Or at least make it "branch_if_not_a57_core".
> Or fix your lr problem by doing "branch_if_a57_core
> apply_a57_core_errata" and having it branch back rather than "ret".
>
> But I think opencoding would be best.  Just define symbols for the
> actual core IDs.
>

How about implementing a table mapping core IDs to entry points (of the
"apply_*_core_errata" fns)
and iterating over that table here? That will make it easy to add new cores
in future too.

Thanks
Arnab

>
> > +WEAK(apply_a57_core_errata)
>
> Why is this weak?
>
> -Scott
>
>
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