From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Schwierzeck Date: Wed, 28 Jan 2015 21:57:30 +0100 Subject: [U-Boot] [PATCH 8/8] MIPS: clear TagLo select 2 during cache init In-Reply-To: <1422284580-2608-9-git-send-email-paul.burton@imgtec.com> References: <1422284580-2608-1-git-send-email-paul.burton@imgtec.com> <1422284580-2608-9-git-send-email-paul.burton@imgtec.com> Message-ID: <54C94D3A.8050809@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Am 26.01.2015 um 16:03 schrieb Paul Burton: > Current MIPS cores from Imagination Technologies use TagLo select 2 for > the data cache. The architecture requires that it is safe for software > to write to this register even if it isn't present, so take the trivial > option of clearing both selects 0 & 2. > > Signed-off-by: Paul Burton > Cc: Daniel Schwierzeck > --- > arch/mips/lib/cache_init.S | 10 ++++++++-- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S > index 04a36b2..137d728 100644 > --- a/arch/mips/lib/cache_init.S > +++ b/arch/mips/lib/cache_init.S > @@ -139,6 +139,14 @@ LEAF(mips_cache_reset) > #endif /* CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD */ > > /* > + * The TagLo registers used depend upon the CPU implementation, but the > + * architecture requires that it is safe for software to write to both > + * TagLo selects 0 & 2 covering supported cases. > + */ > + mtc0 zero, CP0_TAGLO > + mtc0 zero, CP0_TAGLO, 2 maybe we should add new definitions to asm/mipsregs.h. In an out-of-tree SoC port I have something like this #define CP0_ECC $26 #define CP0_CACHEERR $27 #define CP0_TAGLO $28 +#define CP0_ITAGLO $28 +#define CP0_IDATALO $28,1 +#define CP0_DTAGLO $28,2 +#define CP0_DDATALO $28,3 +#define CP0_L23TAGLO $28,4 +#define CP0_L23DATALO $28,5 #define CP0_TAGHI $29 +#define CP0_IDATAHI $29,1 +#define CP0_DTAGHI $29,2 +#define CP0_L23TAGHI $29,4 +#define CP0_L23DATAHI $29,5 #define CP0_ERROREPC $30 #define CP0_DESAVE $31 > + > + /* > * The caches are probably in an indeterminate state, so we force good > * parity into them by doing an invalidate for each line. If > * CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD is set then we'll proceed to > @@ -151,7 +159,6 @@ LEAF(mips_cache_reset) > * Initialize the I-cache first, > */ > blez t2, 1f > - mtc0 zero, CP0_TAGLO > PTR_LI t0, INDEX_BASE > PTR_ADDU t1, t0, t2 > /* clear tag to invalidate */ > @@ -169,7 +176,6 @@ LEAF(mips_cache_reset) > * then initialize D-cache. > */ > 1: blez t3, 3f > - mtc0 zero, CP0_TAGLO > PTR_LI t0, INDEX_BASE > PTR_ADDU t1, t0, t3 > /* clear all tags */ > -- - Daniel