[U-Boot] [PATCH 03/10] arm: socfpga: Sync Cyclone V DK PLL configuration

Marek Vasut
2015-01-30T22:08:43Z

Sync SoCFPGA Cyclone V development kit pinmux configuration with
Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).

NOTE: This change is useless until we get proper SPL support, at
which point this will likely need further rework.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Pavel Machek <pavel@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
---
board/altera/socfpga/pll_config.h | 34 +++++++++++-----------------------
1 file changed, 11 insertions(+), 23 deletions(-)

diff --git a/board/altera/socfpga/pll_config.h b/board/altera/socfpga/pll_config.h
index f0f59a9..8130fa4 100644
--- a/board/altera/socfpga/pll_config.h
+++ b/board/altera/socfpga/pll_config.h
@@ -16,9 +16,9 @@
#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0)
#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0)
#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0)
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (3)
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (3)
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (12)
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (511)
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (511)
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (15)
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK (1)
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1)
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (1)
@@ -36,7 +36,7 @@

/* Peripheral PLL */
#define CONFIG_HPS_PERPLLGRP_VCO_DENOM (1)
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (79)
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (39)
/*
* To tell where is the VCOs source:
* 0 = EOSC1
@@ -45,13 +45,13 @@
*/
#define CONFIG_HPS_PERPLLGRP_VCO_PSRC (0)
#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT (3)
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (3)
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (1)
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (511)
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (511)
#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (4)
#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT (4)
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (9)
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (511)
#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK (0)
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (0)
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (4)
#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (1)
#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (1)
#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (6249)
@@ -66,15 +66,8 @@
#define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1)

/* SDRAM PLL */
-#ifdef CONFIG_SOCFPGA_ARRIA5
-/* Arria V SDRAM will run at 533MHz while Cyclone V still at 400MHz
- * This if..else... is not required if generated by tools */
#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (2)
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (127)
-#else
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (0)
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (31)
-#endif /* CONFIG_SOCFPGA_ARRIA5 */
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (79)

/*
* To tell where is the VCOs source:
@@ -94,17 +87,12 @@

/* Info for driver */
#define CONFIG_HPS_CLK_OSC1_HZ (25000000)
-#define CONFIG_HPS_CLK_OSC2_HZ 0
+#define CONFIG_HPS_CLK_OSC2_HZ (25000000)
#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000)
#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000)
-#ifdef CONFIG_SOCFPGA_ARRIA5
-/* The if..else... is not required if generated by tools */
-#define CONFIG_HPS_CLK_SDRVCO_HZ (1066000000)
-#else
-#define CONFIG_HPS_CLK_SDRVCO_HZ (800000000)
-#endif
+#define CONFIG_HPS_CLK_SDRVCO_HZ (666666666)
#define CONFIG_HPS_CLK_EMAC0_HZ (250000000)
#define CONFIG_HPS_CLK_EMAC1_HZ (250000000)
#define CONFIG_HPS_CLK_USBCLK_HZ (200000000)
--
2.1.3