From mboxrd@z Thu Jan  1 00:00:00 1970
From: York Sun <yorksun@freescale.com>
Date: Mon, 2 Feb 2015 08:40:34 -0600
Subject: [U-Boot] [PATCH v2] arm/ls1021a: Add workaround for DDR erratum
 A008378
In-Reply-To: <20150201031228.7e1e229c@lilith>
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 <20150201031228.7e1e229c@lilith>
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On 01/31/2015 08:12 PM, Albert ARIBAUD wrote:
> Hello York Sun,
> 
> On Wed, 14 Jan 2015 12:46:07 -0800, York Sun <yorksun@freescale.com>
> wrote:
>> Internal memory controller counters can reach a bad state after
>> training in DDR4 mode if accumulated ECC or DBI mode is eanbled.
> 
> typo: eanbled -> enabled.
> 

Thanks for catching it.

York