[U-Boot] [PATCH v6 0/7] Exynos5: Fix warnings and enrich clock_get_periph_rate

[U-Boot] [PATCH v6 0/7] Exynos5: Fix warnings and enrich clock_get_periph_rate

[Akshay Saraswat]

This patch series does following changes -
1. Removing compiler warnings for clock_get_periph_rate.
2. Adding and enabling support for Exynos542x in
   clock_get_periph_rate.
3. Replacing peripheral specific function calls with
   clock_get_periph_rate.
4. Remove code from clocks file which became useless due to
   introduction of clock_get_periph_rate.

Changes since v5:
	- Elaborated commit message and fixed a nit.

Changes since v4:
	- Added Reviewed-by in patches 3 and 5.
	- Split patch 6 of version 4 into two patches 6 and 7.

Changes since v3:
	- Added Reviewed-by & Tested-by in patches 1, 2 and 4.
	- Patch-3: Handled SPLL case in exynos542x_get_periph_rate.
	- Patch-3: Changed EXYNOS542x -> EXYNOS542X in pll_src_bit enum.
	- Merged pathces 5 and 6 of version 3.
	- Patch-6: New patch for dealing with variety of mask bits.

Changes since v2:
	- Patch-1: Added debug message for unknown periph IDs.
	- Patch-2: Changed exynos5420 -> exynos542x in comment.
	- Patch-3: Fixed enum and soc_get_periph_rate switch.
	- Patch-3: Added checks for negative values in soc_get_periph_rate.
	- Patch-4: Added checks for negative values in soc_get_periph_rate.

Changes since v1:
	- Added 2 new patches.


Akshay Saraswat (7):
  Exynos5: Fix compiler warnings due to clock_get_periph_rate
  Exynos542x: Move exynos5420_get_pll_clk up and rename
  Exynos542x: Add and enable get_periph_rate support
  Exynos5: Fix exynos5_get_periph_rate calculations
  Exynos5: Use clock_get_periph_rate generic API
  Exynos: clock: change mask bits as per peripheral
  Exynos: Clock: Cleanup soc_get_periph_rate

 arch/arm/cpu/armv7/exynos/clock.c      | 617 ++++++++++++++++-----------------
 arch/arm/include/asm/arch-exynos/clk.h |   4 +
 2 files changed, 298 insertions(+), 323 deletions(-)

-- 
1.9.1

[U-Boot] [PATCH v6 1/7] Exynos5: Fix compiler warnings due to clock_get_periph_rate

[Akshay Saraswat]

Apparently, members of clk_bit_info array do not map correctly
to the members of enum periph_id. This mapping got broken after
we changed periph_id(s) to reflect interrupt number instead of
their position in a sequence. This patch intends to fix above
mentioned issue.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
---
Changes since v5:
	- No Change.

Changes since v4:
	- No Change.

Changes since v3:
	- Added Reviewed-by & Tested-by.

Changes since v2:
	- Added debug message for unknown periph IDs.

Changes since v1:
	- Removed exynos5_bit_info array name.

 arch/arm/cpu/armv7/exynos/clock.c | 80 ++++++++++++++++++++++++---------------
 1 file changed, 49 insertions(+), 31 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index b31c13b..6f20c81 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -20,42 +20,45 @@
  * positions of the peripheral clocks of the src and div registers
  */
 struct clk_bit_info {
+	enum periph_id id;
 	int8_t src_bit;
 	int8_t div_bit;
 	int8_t prediv_bit;
 };
 
-/* src_bit div_bit prediv_bit */
+/* periph_id src_bit div_bit prediv_bit */
 static struct clk_bit_info clk_bit_info[] = {
-	{0,	0,	-1},
-	{4,	4,	-1},
-	{8,	8,	-1},
-	{12,	12,	-1},
-	{0,	0,	8},
-	{4,	16,	24},
-	{8,	0,	8},
-	{12,	16,	24},
-	{-1,	-1,	-1},
-	{16,	0,	8},
-	{20,	16,	24},
-	{24,	0,	8},
-	{0,	0,	4},
-	{4,	12,	16},
-	{-1,	-1,	-1},
-	{-1,	-1,	-1},
-	{-1,	24,	0},
-	{-1,	24,	0},
-	{-1,	24,	0},
-	{-1,	24,	0},
-	{-1,	24,	0},
-	{-1,	24,	0},
-	{-1,	24,	0},
-	{-1,	24,	0},
-	{24,	0,	-1},
-	{24,	0,	-1},
-	{24,	0,	-1},
-	{24,	0,	-1},
-	{24,	0,	-1},
+	{PERIPH_ID_UART0,	0,	0,	-1},
+	{PERIPH_ID_UART1,	4,	4,	-1},
+	{PERIPH_ID_UART2,	8,	8,	-1},
+	{PERIPH_ID_UART3,	12,	12,	-1},
+	{PERIPH_ID_I2C0,	-1,	24,	0},
+	{PERIPH_ID_I2C1,	-1,	24,	0},
+	{PERIPH_ID_I2C2,	-1,	24,	0},
+	{PERIPH_ID_I2C3,	-1,	24,	0},
+	{PERIPH_ID_I2C4,	-1,	24,	0},
+	{PERIPH_ID_I2C5,	-1,	24,	0},
+	{PERIPH_ID_I2C6,	-1,	24,	0},
+	{PERIPH_ID_I2C7,	-1,	24,	0},
+	{PERIPH_ID_SPI0,	16,	0,	8},
+	{PERIPH_ID_SPI1,	20,	16,	24},
+	{PERIPH_ID_SPI2,	24,	0,	8},
+	{PERIPH_ID_SDMMC0,	0,	0,	8},
+	{PERIPH_ID_SDMMC1,	4,	16,	24},
+	{PERIPH_ID_SDMMC2,	8,	0,	8},
+	{PERIPH_ID_SDMMC3,	12,	16,	24},
+	{PERIPH_ID_I2S0,	0,	0,	4},
+	{PERIPH_ID_I2S1,	4,	12,	16},
+	{PERIPH_ID_SPI3,	0,	0,	4},
+	{PERIPH_ID_SPI4,	4,	12,	16},
+	{PERIPH_ID_SDMMC4,	16,	0,	8},
+	{PERIPH_ID_PWM0,	24,	0,	-1},
+	{PERIPH_ID_PWM1,	24,	0,	-1},
+	{PERIPH_ID_PWM2,	24,	0,	-1},
+	{PERIPH_ID_PWM3,	24,	0,	-1},
+	{PERIPH_ID_PWM4,	24,	0,	-1},
+
+	{PERIPH_ID_NONE,	-1,	-1,	-1},
 };
 
 /* Epll Clock division values to achive different frequency output */
@@ -260,9 +263,24 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
 	return fout;
 }
 
+static struct clk_bit_info *get_clk_bit_info(int peripheral)
+{
+	int i;
+
+	for (i = 0; clk_bit_info[i].id != PERIPH_ID_NONE; i++) {
+		if (clk_bit_info[i].id == peripheral)
+			break;
+	}
+
+	if (clk_bit_info[i].id == PERIPH_ID_NONE)
+		debug("ERROR: Peripheral ID %d not found\n", peripheral);
+
+	return &clk_bit_info[i];
+}
+
 static unsigned long exynos5_get_periph_rate(int peripheral)
 {
-	struct clk_bit_info *bit_info = &clk_bit_info[peripheral];
+	struct clk_bit_info *bit_info = get_clk_bit_info(peripheral);
 	unsigned long sclk, sub_clk;
 	unsigned int src, div, sub_div;
 	struct exynos5_clock *clk =
-- 
1.9.1

[U-Boot] [PATCH v6 2/7] Exynos542x: Move exynos5420_get_pll_clk up and rename

[Akshay Saraswat]

Moving exynos5420_get_pll_clk function definition up in the
code to keep it together with rest of SoC_get_pll_clk functions.
This makes code more legible and also removes the need of
declaration when called before the position of definition in
code. Also, renaming exynos5420_get_pll_clk to
exynos542x_get_pll_clk because it is being used for both Exynos
5420 and 5800.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
---
Changes since v5:
	- No Change.

Changes since v4:
	- No Change.

Changes since v3:
	- Added Reviewed-by & Tested-by.

Changes since v2:
	- Changed exynos5420 -> exynos542x in line 33.

Changes since v1:
	- New patch.

 arch/arm/cpu/armv7/exynos/clock.c | 82 +++++++++++++++++++--------------------
 1 file changed, 41 insertions(+), 41 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index 6f20c81..5dc9ed2 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -263,6 +263,46 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
 	return fout;
 }
 
+/* exynos542x: return pll clock frequency */
+static unsigned long exynos542x_get_pll_clk(int pllreg)
+{
+	struct exynos5420_clock *clk =
+		(struct exynos5420_clock *)samsung_get_base_clock();
+	unsigned long r, k = 0;
+
+	switch (pllreg) {
+	case APLL:
+		r = readl(&clk->apll_con0);
+		break;
+	case MPLL:
+		r = readl(&clk->mpll_con0);
+		break;
+	case EPLL:
+		r = readl(&clk->epll_con0);
+		k = readl(&clk->epll_con1);
+		break;
+	case VPLL:
+		r = readl(&clk->vpll_con0);
+		k = readl(&clk->vpll_con1);
+		break;
+	case BPLL:
+		r = readl(&clk->bpll_con0);
+		break;
+	case RPLL:
+		r = readl(&clk->rpll_con0);
+		k = readl(&clk->rpll_con1);
+		break;
+	case SPLL:
+		r = readl(&clk->spll_con0);
+		break;
+	default:
+		printf("Unsupported PLL (%d)\n", pllreg);
+		return 0;
+	}
+
+	return exynos_get_pll_clk(pllreg, r, k);
+}
+
 static struct clk_bit_info *get_clk_bit_info(int peripheral)
 {
 	int i;
@@ -382,46 +422,6 @@ unsigned long clock_get_periph_rate(int peripheral)
 		return 0;
 }
 
-/* exynos5420: return pll clock frequency */
-static unsigned long exynos5420_get_pll_clk(int pllreg)
-{
-	struct exynos5420_clock *clk =
-		(struct exynos5420_clock *)samsung_get_base_clock();
-	unsigned long r, k = 0;
-
-	switch (pllreg) {
-	case APLL:
-		r = readl(&clk->apll_con0);
-		break;
-	case MPLL:
-		r = readl(&clk->mpll_con0);
-		break;
-	case EPLL:
-		r = readl(&clk->epll_con0);
-		k = readl(&clk->epll_con1);
-		break;
-	case VPLL:
-		r = readl(&clk->vpll_con0);
-		k = readl(&clk->vpll_con1);
-		break;
-	case BPLL:
-		r = readl(&clk->bpll_con0);
-		break;
-	case RPLL:
-		r = readl(&clk->rpll_con0);
-		k = readl(&clk->rpll_con1);
-		break;
-	case SPLL:
-		r = readl(&clk->spll_con0);
-		break;
-	default:
-		printf("Unsupported PLL (%d)\n", pllreg);
-		return 0;
-	}
-
-	return exynos_get_pll_clk(pllreg, r, k);
-}
-
 /* exynos4: return ARM clock frequency */
 static unsigned long exynos4_get_arm_clk(void)
 {
@@ -1603,7 +1603,7 @@ unsigned long get_pll_clk(int pllreg)
 {
 	if (cpu_is_exynos5()) {
 		if (proid_is_exynos5420() || proid_is_exynos5800())
-			return exynos5420_get_pll_clk(pllreg);
+			return exynos542x_get_pll_clk(pllreg);
 		return exynos5_get_pll_clk(pllreg);
 	} else {
 		if (proid_is_exynos4412())
-- 
1.9.1

[U-Boot] [PATCH v6 3/7] Exynos542x: Add and enable get_periph_rate support

[Akshay Saraswat]

We planned to fetch peripheral rate through one generic API per
peripheral. These generic peripheral functions are in turn
expected to fetch apt values from a function refactored as
per SoC versions. This patch adds support for fetching peripheral
rates for Exynos5420 and Exynos5800.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
Changes since v5:
	- No Change.

Changes since v4:
	- Added Reviewed-by.

Changes since v3:
	- Added a case for SPLL in exynos542x_get_periph_rate.
	- Changed EXYNOS542x -> EXYNOS542X.

Changes since v2:
	- Fixed enum and exynos542x_get_periph_rate switch.
	- Added checks for negative values in exynos542x_get_periph_rate.

Changes since v1:
	- Changes suuport -> support in commit message.
	- Removed position change of exynos5420_get_pll_clk.
	- Removed #ifdef.

 arch/arm/cpu/armv7/exynos/clock.c      | 153 +++++++++++++++++++++++++++++++--
 arch/arm/include/asm/arch-exynos/clk.h |   4 +
 2 files changed, 150 insertions(+), 7 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index 5dc9ed2..16900cc 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -27,7 +27,7 @@ struct clk_bit_info {
 };
 
 /* periph_id src_bit div_bit prediv_bit */
-static struct clk_bit_info clk_bit_info[] = {
+static struct clk_bit_info exynos5_bit_info[] = {
 	{PERIPH_ID_UART0,	0,	0,	-1},
 	{PERIPH_ID_UART1,	4,	4,	-1},
 	{PERIPH_ID_UART2,	8,	8,	-1},
@@ -61,6 +61,41 @@ static struct clk_bit_info clk_bit_info[] = {
 	{PERIPH_ID_NONE,	-1,	-1,	-1},
 };
 
+static struct clk_bit_info exynos542x_bit_info[] = {
+	{PERIPH_ID_UART0,	4,	8,	-1},
+	{PERIPH_ID_UART1,	8,	12,	-1},
+	{PERIPH_ID_UART2,	12,	16,	-1},
+	{PERIPH_ID_UART3,	16,	20,	-1},
+	{PERIPH_ID_I2C0,	-1,	8,	-1},
+	{PERIPH_ID_I2C1,	-1,	8,	-1},
+	{PERIPH_ID_I2C2,	-1,	8,	-1},
+	{PERIPH_ID_I2C3,	-1,	8,	-1},
+	{PERIPH_ID_I2C4,	-1,	8,	-1},
+	{PERIPH_ID_I2C5,	-1,	8,	-1},
+	{PERIPH_ID_I2C6,	-1,	8,	-1},
+	{PERIPH_ID_I2C7,	-1,	8,	-1},
+	{PERIPH_ID_SPI0,	20,	20,	8},
+	{PERIPH_ID_SPI1,	24,	24,	16},
+	{PERIPH_ID_SPI2,	28,	28,	24},
+	{PERIPH_ID_SDMMC0,	8,	0,	-1},
+	{PERIPH_ID_SDMMC1,	12,	10,	-1},
+	{PERIPH_ID_SDMMC2,	16,	20,	-1},
+	{PERIPH_ID_I2C8,	-1,	8,	-1},
+	{PERIPH_ID_I2C9,	-1,	8,	-1},
+	{PERIPH_ID_I2S0,	0,	0,	4},
+	{PERIPH_ID_I2S1,	4,	12,	16},
+	{PERIPH_ID_SPI3,	12,	16,	0},
+	{PERIPH_ID_SPI4,	16,	20,	8},
+	{PERIPH_ID_PWM0,	24,	28,	-1},
+	{PERIPH_ID_PWM1,	24,	28,	-1},
+	{PERIPH_ID_PWM2,	24,	28,	-1},
+	{PERIPH_ID_PWM3,	24,	28,	-1},
+	{PERIPH_ID_PWM4,	24,	28,	-1},
+	{PERIPH_ID_I2C10,	-1,	8,	-1},
+
+	{PERIPH_ID_NONE,	-1,	-1,	-1},
+};
+
 /* Epll Clock division values to achive different frequency output */
 static struct set_epll_con_val exynos5_epll_div[] = {
 	{ 192000000, 0, 48, 3, 1, 0 },
@@ -306,16 +341,22 @@ static unsigned long exynos542x_get_pll_clk(int pllreg)
 static struct clk_bit_info *get_clk_bit_info(int peripheral)
 {
 	int i;
+	struct clk_bit_info *info;
+
+	if (proid_is_exynos5420() || proid_is_exynos5800())
+		info = exynos542x_bit_info;
+	else
+		info = exynos5_bit_info;
 
-	for (i = 0; clk_bit_info[i].id != PERIPH_ID_NONE; i++) {
-		if (clk_bit_info[i].id == peripheral)
+	for (i = 0; info[i].id != PERIPH_ID_NONE; i++) {
+		if (info[i].id == peripheral)
 			break;
 	}
 
-	if (clk_bit_info[i].id == PERIPH_ID_NONE)
+	if (info[i].id == PERIPH_ID_NONE)
 		debug("ERROR: Peripheral ID %d not found\n", peripheral);
 
-	return &clk_bit_info[i];
+	return &info[i];
 }
 
 static unsigned long exynos5_get_periph_rate(int peripheral)
@@ -414,12 +455,110 @@ static unsigned long exynos5_get_periph_rate(int peripheral)
 	return sub_clk;
 }
 
+static unsigned long exynos542x_get_periph_rate(int peripheral)
+{
+	struct clk_bit_info *bit_info = get_clk_bit_info(peripheral);
+	unsigned long sclk, sub_clk = 0;
+	unsigned int src, div, sub_div = 0;
+	struct exynos5420_clock *clk =
+			(struct exynos5420_clock *)samsung_get_base_clock();
+
+	switch (peripheral) {
+	case PERIPH_ID_UART0:
+	case PERIPH_ID_UART1:
+	case PERIPH_ID_UART2:
+	case PERIPH_ID_UART3:
+	case PERIPH_ID_PWM0:
+	case PERIPH_ID_PWM1:
+	case PERIPH_ID_PWM2:
+	case PERIPH_ID_PWM3:
+	case PERIPH_ID_PWM4:
+		src = readl(&clk->src_peric0);
+		div = readl(&clk->div_peric0);
+		break;
+	case PERIPH_ID_SPI0:
+	case PERIPH_ID_SPI1:
+	case PERIPH_ID_SPI2:
+		src = readl(&clk->src_peric1);
+		div = readl(&clk->div_peric1);
+		sub_div = readl(&clk->div_peric4);
+		break;
+	case PERIPH_ID_SPI3:
+	case PERIPH_ID_SPI4:
+		src = readl(&clk->src_isp);
+		div = readl(&clk->div_isp1);
+		sub_div = readl(&clk->div_isp1);
+		break;
+	case PERIPH_ID_SDMMC0:
+	case PERIPH_ID_SDMMC1:
+	case PERIPH_ID_SDMMC2:
+	case PERIPH_ID_SDMMC3:
+		src = readl(&clk->src_fsys);
+		div = readl(&clk->div_fsys1);
+		break;
+	case PERIPH_ID_I2C0:
+	case PERIPH_ID_I2C1:
+	case PERIPH_ID_I2C2:
+	case PERIPH_ID_I2C3:
+	case PERIPH_ID_I2C4:
+	case PERIPH_ID_I2C5:
+	case PERIPH_ID_I2C6:
+	case PERIPH_ID_I2C7:
+	case PERIPH_ID_I2C8:
+	case PERIPH_ID_I2C9:
+	case PERIPH_ID_I2C10:
+		sclk = exynos542x_get_pll_clk(MPLL);
+		sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit)
+								& 0x7) + 1;
+		return sclk / sub_div;
+	default:
+		debug("%s: invalid peripheral %d", __func__, peripheral);
+		return -1;
+	};
+
+	if (bit_info->src_bit >= 0)
+		src = (src >> bit_info->src_bit) & 0xf;
+
+	switch (src) {
+	case EXYNOS542X_SRC_MPLL:
+		sclk = exynos542x_get_pll_clk(MPLL);
+		break;
+	case EXYNOS542X_SRC_SPLL:
+		sclk = exynos542x_get_pll_clk(SPLL);
+		break;
+	case EXYNOS542X_SRC_EPLL:
+		sclk = exynos542x_get_pll_clk(EPLL);
+		break;
+	case EXYNOS542X_SRC_RPLL:
+		sclk = exynos542x_get_pll_clk(RPLL);
+		break;
+	default:
+		return 0;
+	}
+
+	/* Ratio clock division for this peripheral */
+	if (bit_info->div_bit >= 0) {
+		div = (div >> bit_info->div_bit) & 0xf;
+		sub_clk = sclk / (div + 1);
+	}
+
+	if (bit_info->prediv_bit >= 0) {
+		sub_div = (sub_div >> bit_info->prediv_bit) & 0xff;
+		return sub_clk / (sub_div + 1);
+	}
+
+	return sub_clk;
+}
+
 unsigned long clock_get_periph_rate(int peripheral)
 {
-	if (cpu_is_exynos5())
+	if (cpu_is_exynos5()) {
+		if (proid_is_exynos5420() || proid_is_exynos5800())
+			return exynos542x_get_periph_rate(peripheral);
 		return exynos5_get_periph_rate(peripheral);
-	else
+	} else {
 		return 0;
+	}
 }
 
 /* exynos4: return ARM clock frequency */
diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h
index db24dc0..2a17dfc 100644
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -26,6 +26,10 @@ enum pll_src_bit {
 	EXYNOS_SRC_MPLL = 6,
 	EXYNOS_SRC_EPLL,
 	EXYNOS_SRC_VPLL,
+	EXYNOS542X_SRC_MPLL = 3,
+	EXYNOS542X_SRC_SPLL,
+	EXYNOS542X_SRC_EPLL = 6,
+	EXYNOS542X_SRC_RPLL,
 };
 
 unsigned long get_pll_clk(int pllreg);
-- 
1.9.1

[U-Boot] [PATCH v6 4/7] Exynos5: Fix exynos5_get_periph_rate calculations

[Akshay Saraswat]

exynos5_get_periph_rate function reads incorrect div for
SDMMC2 & 3. It also reads prediv and does division only for
SDMMC0 & 2 when actually various other peripherals need that.
Adding changes to fix these mistakes in periph rate calculation.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
---
Changes since v5:
	- No Change.

Changes since v4:
	- No Change.

Changes since v3:
	- Added Reviewed-by & Tested-by.

Changes since v2:
	- Added checks for negative values in exynos5_get_periph_rate.

Changes since v1:
	- New patch.

 arch/arm/cpu/armv7/exynos/clock.c | 21 +++++++++++++--------
 1 file changed, 13 insertions(+), 8 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index 16900cc..78f784a 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -362,8 +362,8 @@ static struct clk_bit_info *get_clk_bit_info(int peripheral)
 static unsigned long exynos5_get_periph_rate(int peripheral)
 {
 	struct clk_bit_info *bit_info = get_clk_bit_info(peripheral);
-	unsigned long sclk, sub_clk;
-	unsigned int src, div, sub_div;
+	unsigned long sclk, sub_clk = 0;
+	unsigned int src, div, sub_div = 0;
 	struct exynos5_clock *clk =
 			(struct exynos5_clock *)samsung_get_base_clock();
 
@@ -402,10 +402,13 @@ static unsigned long exynos5_get_periph_rate(int peripheral)
 		break;
 	case PERIPH_ID_SDMMC0:
 	case PERIPH_ID_SDMMC1:
+		src = readl(&clk->src_fsys);
+		div = readl(&clk->div_fsys1);
+		break;
 	case PERIPH_ID_SDMMC2:
 	case PERIPH_ID_SDMMC3:
 		src = readl(&clk->src_fsys);
-		div = readl(&clk->div_fsys1);
+		div = readl(&clk->div_fsys2);
 		break;
 	case PERIPH_ID_I2C0:
 	case PERIPH_ID_I2C1:
@@ -426,7 +429,8 @@ static unsigned long exynos5_get_periph_rate(int peripheral)
 		return -1;
 	};
 
-	src = (src >> bit_info->src_bit) & 0xf;
+	if (bit_info->src_bit >= 0)
+		src = (src >> bit_info->src_bit) & 0xf;
 
 	switch (src) {
 	case EXYNOS_SRC_MPLL:
@@ -443,11 +447,12 @@ static unsigned long exynos5_get_periph_rate(int peripheral)
 	}
 
 	/* Ratio clock division for this peripheral */
-	sub_div = (div >> bit_info->div_bit) & 0xf;
-	sub_clk = sclk / (sub_div + 1);
+	if (bit_info->div_bit >= 0) {
+		sub_div = (div >> bit_info->div_bit) & 0xf;
+		sub_clk = sclk / (sub_div + 1);
+	}
 
-	/* Pre-ratio clock division for SDMMC0 and 2 */
-	if (peripheral == PERIPH_ID_SDMMC0 || peripheral == PERIPH_ID_SDMMC2) {
+	if (bit_info->prediv_bit >= 0) {
 		div = (div >> bit_info->prediv_bit) & 0xff;
 		return sub_clk / (div + 1);
 	}
-- 
1.9.1

[U-Boot] [PATCH v6 5/7] Exynos5: Use clock_get_periph_rate generic API

[Akshay Saraswat]

Replacing SoC and peripheral specific function calls with generic
clock_get_periph_rate calls to get the peripheral clocks.
Also, removing dead code of peripheral and SoC specific function
implementations which was used earlier for fetching peripheral clocks.
This code is not being used anymore because of the introduction
of generic clock_get_periph_rate function.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
Changes since v5:
	- No Change.

Changes since v4:
	- Added Reviewed-by.

Changes since v3:
	- Merged patches 5 and 6 of version 3 to fix build errors.

Changes since v2:
	- No change.

Changes since v1:
	- Separated exynos5_get_periph_rate fixes into another patch.

 arch/arm/cpu/armv7/exynos/clock.c | 278 ++++++--------------------------------
 1 file changed, 43 insertions(+), 235 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index 78f784a..f19fb5c 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -689,27 +689,6 @@ static unsigned long exynos4x12_get_pwm_clk(void)
 	return pclk;
 }
 
-/* exynos5420: return pwm clock frequency */
-static unsigned long exynos5420_get_pwm_clk(void)
-{
-	struct exynos5420_clock *clk =
-		(struct exynos5420_clock *)samsung_get_base_clock();
-	unsigned long pclk, sclk;
-	unsigned int ratio;
-
-	/*
-	 * CLK_DIV_PERIC0
-	 * PWM_RATIO [31:28]
-	 */
-	ratio = readl(&clk->div_peric0);
-	ratio = (ratio >> 28) & 0xf;
-	sclk = get_pll_clk(MPLL);
-
-	pclk = sclk / (ratio + 1);
-
-	return pclk;
-}
-
 /* exynos4: return uart clock frequency */
 static unsigned long exynos4_get_uart_clk(int dev_index)
 {
@@ -802,100 +781,6 @@ static unsigned long exynos4x12_get_uart_clk(int dev_index)
 	return uclk;
 }
 
-/* exynos5: return uart clock frequency */
-static unsigned long exynos5_get_uart_clk(int dev_index)
-{
-	struct exynos5_clock *clk =
-		(struct exynos5_clock *)samsung_get_base_clock();
-	unsigned long uclk, sclk;
-	unsigned int sel;
-	unsigned int ratio;
-
-	/*
-	 * CLK_SRC_PERIC0
-	 * UART0_SEL [3:0]
-	 * UART1_SEL [7:4]
-	 * UART2_SEL [8:11]
-	 * UART3_SEL [12:15]
-	 * UART4_SEL [16:19]
-	 * UART5_SEL [23:20]
-	 */
-	sel = readl(&clk->src_peric0);
-	sel = (sel >> (dev_index << 2)) & 0xf;
-
-	if (sel == 0x6)
-		sclk = get_pll_clk(MPLL);
-	else if (sel == 0x7)
-		sclk = get_pll_clk(EPLL);
-	else if (sel == 0x8)
-		sclk = get_pll_clk(VPLL);
-	else
-		return 0;
-
-	/*
-	 * CLK_DIV_PERIC0
-	 * UART0_RATIO [3:0]
-	 * UART1_RATIO [7:4]
-	 * UART2_RATIO [8:11]
-	 * UART3_RATIO [12:15]
-	 * UART4_RATIO [16:19]
-	 * UART5_RATIO [23:20]
-	 */
-	ratio = readl(&clk->div_peric0);
-	ratio = (ratio >> (dev_index << 2)) & 0xf;
-
-	uclk = sclk / (ratio + 1);
-
-	return uclk;
-}
-
-/* exynos5420: return uart clock frequency */
-static unsigned long exynos5420_get_uart_clk(int dev_index)
-{
-	struct exynos5420_clock *clk =
-		(struct exynos5420_clock *)samsung_get_base_clock();
-	unsigned long uclk, sclk;
-	unsigned int sel;
-	unsigned int ratio;
-
-	/*
-	 * CLK_SRC_PERIC0
-	 * UART0_SEL [6:4]
-	 * UART1_SEL [10:8]
-	 * UART2_SEL [14:12]
-	 * UART3_SEL [18:16]
-	 * generalised calculation as follows
-	 * sel = (sel >> ((dev_index * 4) + 4)) & mask;
-	 */
-	sel = readl(&clk->src_peric0);
-	sel = (sel >> ((dev_index * 4) + 4)) & 0x7;
-
-	if (sel == 0x3)
-		sclk = get_pll_clk(MPLL);
-	else if (sel == 0x6)
-		sclk = get_pll_clk(EPLL);
-	else if (sel == 0x7)
-		sclk = get_pll_clk(RPLL);
-	else
-		return 0;
-
-	/*
-	 * CLK_DIV_PERIC0
-	 * UART0_RATIO [11:8]
-	 * UART1_RATIO [15:12]
-	 * UART2_RATIO [19:16]
-	 * UART3_RATIO [23:20]
-	 * generalised calculation as follows
-	 * ratio = (ratio >> ((dev_index * 4) + 8)) & mask;
-	 */
-	ratio = readl(&clk->div_peric0);
-	ratio = (ratio >> ((dev_index * 4) + 8)) & 0xf;
-
-	uclk = sclk / (ratio + 1);
-
-	return uclk;
-}
-
 static unsigned long exynos4_get_mmc_clk(int dev_index)
 {
 	struct exynos4_clock *clk =
@@ -945,94 +830,6 @@ static unsigned long exynos4_get_mmc_clk(int dev_index)
 	return uclk;
 }
 
-static unsigned long exynos5_get_mmc_clk(int dev_index)
-{
-	struct exynos5_clock *clk =
-		(struct exynos5_clock *)samsung_get_base_clock();
-	unsigned long uclk, sclk;
-	unsigned int sel, ratio, pre_ratio;
-	int shift = 0;
-
-	sel = readl(&clk->src_fsys);
-	sel = (sel >> (dev_index << 2)) & 0xf;
-
-	if (sel == 0x6)
-		sclk = get_pll_clk(MPLL);
-	else if (sel == 0x7)
-		sclk = get_pll_clk(EPLL);
-	else if (sel == 0x8)
-		sclk = get_pll_clk(VPLL);
-	else
-		return 0;
-
-	switch (dev_index) {
-	case 0:
-	case 1:
-		ratio = readl(&clk->div_fsys1);
-		pre_ratio = readl(&clk->div_fsys1);
-		break;
-	case 2:
-	case 3:
-		ratio = readl(&clk->div_fsys2);
-		pre_ratio = readl(&clk->div_fsys2);
-		break;
-	default:
-		return 0;
-	}
-
-	if (dev_index == 1 || dev_index == 3)
-		shift = 16;
-
-	ratio = (ratio >> shift) & 0xf;
-	pre_ratio = (pre_ratio >> (shift + 8)) & 0xff;
-	uclk = (sclk / (ratio + 1)) / (pre_ratio + 1);
-
-	return uclk;
-}
-
-static unsigned long exynos5420_get_mmc_clk(int dev_index)
-{
-	struct exynos5420_clock *clk =
-		(struct exynos5420_clock *)samsung_get_base_clock();
-	unsigned long uclk, sclk;
-	unsigned int sel, ratio;
-
-	/*
-	 * CLK_SRC_FSYS
-	 * MMC0_SEL [10:8]
-	 * MMC1_SEL [14:12]
-	 * MMC2_SEL [18:16]
-	 * generalised calculation as follows
-	 * sel = (sel >> ((dev_index * 4) + 8)) & mask
-	 */
-	sel = readl(&clk->src_fsys);
-	sel = (sel >> ((dev_index * 4) + 8)) & 0x7;
-
-	if (sel == 0x3)
-		sclk = get_pll_clk(MPLL);
-	else if (sel == 0x4)
-		sclk = get_pll_clk(SPLL);
-	else if (sel == 0x6)
-		sclk = get_pll_clk(EPLL);
-	else
-		return 0;
-
-	/*
-	 * CLK_DIV_FSYS1
-	 * MMC0_RATIO [9:0]
-	 * MMC1_RATIO [19:10]
-	 * MMC2_RATIO [29:20]
-	 * generalised calculation as follows
-	 * ratio = (ratio >> (dev_index * 10)) & mask
-	 */
-	ratio = readl(&clk->div_fsys1);
-	ratio = (ratio >> (dev_index * 10)) & 0x3ff;
-
-	uclk = (sclk / (ratio + 1));
-
-	return uclk;
-}
-
 /* exynos4: set the mmc clock */
 static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
 {
@@ -1411,29 +1208,6 @@ void exynos4_set_mipi_clk(void)
 	clrsetbits_le32(&clk->div_lcd0, 0xf << 16, 0x1 << 16);
 }
 
-/*
- * I2C
- *
- * exynos5: obtaining the I2C clock
- */
-static unsigned long exynos5_get_i2c_clk(void)
-{
-	struct exynos5_clock *clk =
-		(struct exynos5_clock *)samsung_get_base_clock();
-	unsigned long aclk_66, aclk_66_pre, sclk;
-	unsigned int ratio;
-
-	sclk = get_pll_clk(MPLL);
-
-	ratio = (readl(&clk->div_top1)) >> 24;
-	ratio &= 0x7;
-	aclk_66_pre = sclk / (ratio + 1);
-	ratio = readl(&clk->div_top0);
-	ratio &= 0x7;
-	aclk_66 = aclk_66_pre / (ratio + 1);
-	return aclk_66;
-}
-
 int exynos5_set_epll_clk(unsigned long rate)
 {
 	unsigned int epll_con, epll_con_k;
@@ -1770,7 +1544,7 @@ unsigned long get_arm_clk(void)
 unsigned long get_i2c_clk(void)
 {
 	if (cpu_is_exynos5()) {
-		return exynos5_get_i2c_clk();
+		return clock_get_periph_rate(PERIPH_ID_I2C0);
 	} else if (cpu_is_exynos4()) {
 		return exynos4_get_i2c_clk();
 	} else {
@@ -1782,8 +1556,6 @@ unsigned long get_i2c_clk(void)
 unsigned long get_pwm_clk(void)
 {
 	if (cpu_is_exynos5()) {
-		if (proid_is_exynos5420() || proid_is_exynos5800())
-			return exynos5420_get_pwm_clk();
 		return clock_get_periph_rate(PERIPH_ID_PWM0);
 	} else {
 		if (proid_is_exynos4412())
@@ -1794,10 +1566,28 @@ unsigned long get_pwm_clk(void)
 
 unsigned long get_uart_clk(int dev_index)
 {
+	enum periph_id id;
+
+	switch (dev_index) {
+	case 0:
+		id = PERIPH_ID_UART0;
+		break;
+	case 1:
+		id = PERIPH_ID_UART1;
+		break;
+	case 2:
+		id = PERIPH_ID_UART2;
+		break;
+	case 3:
+		id = PERIPH_ID_UART3;
+		break;
+	default:
+		debug("%s: invalid UART index %d", __func__, dev_index);
+		return -1;
+	}
+
 	if (cpu_is_exynos5()) {
-		if (proid_is_exynos5420() || proid_is_exynos5800())
-			return exynos5420_get_uart_clk(dev_index);
-		return exynos5_get_uart_clk(dev_index);
+		return clock_get_periph_rate(id);
 	} else {
 		if (proid_is_exynos4412())
 			return exynos4x12_get_uart_clk(dev_index);
@@ -1807,10 +1597,28 @@ unsigned long get_uart_clk(int dev_index)
 
 unsigned long get_mmc_clk(int dev_index)
 {
+	enum periph_id id;
+
+	switch (dev_index) {
+	case 0:
+		id = PERIPH_ID_SDMMC0;
+		break;
+	case 1:
+		id = PERIPH_ID_SDMMC1;
+		break;
+	case 2:
+		id = PERIPH_ID_SDMMC2;
+		break;
+	case 3:
+		id = PERIPH_ID_SDMMC3;
+		break;
+	default:
+		debug("%s: invalid MMC index %d", __func__, dev_index);
+		return -1;
+	}
+
 	if (cpu_is_exynos5()) {
-		if (proid_is_exynos5420() || proid_is_exynos5800())
-			return exynos5420_get_mmc_clk(dev_index);
-		return exynos5_get_mmc_clk(dev_index);
+		return clock_get_periph_rate(id);
 	} else {
 		return exynos4_get_mmc_clk(dev_index);
 	}
-- 
1.9.1

[U-Boot] [PATCH v6 6/7] Exynos: clock: change mask bits as per peripheral

[Akshay Saraswat]

We have assumed and kept mask bits for divider and pre-divider
as 0xf and 0xff, respectively. But these mask bits change from
one peripheral to another, and hence, need to be specified in
accordance with the peripherals.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
---
Changes since v5:
	- No Change.

Changes since v4:
	- Isolated maskbit changes.

Changes since v3:
	- New patch.

 arch/arm/cpu/armv7/exynos/clock.c | 151 ++++++++++++++++++++------------------
 1 file changed, 78 insertions(+), 73 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index f19fb5c..3884d4b 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -21,79 +21,83 @@
  */
 struct clk_bit_info {
 	enum periph_id id;
+	int32_t src_mask;
+	int32_t div_mask;
+	int32_t prediv_mask;
 	int8_t src_bit;
 	int8_t div_bit;
 	int8_t prediv_bit;
 };
 
-/* periph_id src_bit div_bit prediv_bit */
 static struct clk_bit_info exynos5_bit_info[] = {
-	{PERIPH_ID_UART0,	0,	0,	-1},
-	{PERIPH_ID_UART1,	4,	4,	-1},
-	{PERIPH_ID_UART2,	8,	8,	-1},
-	{PERIPH_ID_UART3,	12,	12,	-1},
-	{PERIPH_ID_I2C0,	-1,	24,	0},
-	{PERIPH_ID_I2C1,	-1,	24,	0},
-	{PERIPH_ID_I2C2,	-1,	24,	0},
-	{PERIPH_ID_I2C3,	-1,	24,	0},
-	{PERIPH_ID_I2C4,	-1,	24,	0},
-	{PERIPH_ID_I2C5,	-1,	24,	0},
-	{PERIPH_ID_I2C6,	-1,	24,	0},
-	{PERIPH_ID_I2C7,	-1,	24,	0},
-	{PERIPH_ID_SPI0,	16,	0,	8},
-	{PERIPH_ID_SPI1,	20,	16,	24},
-	{PERIPH_ID_SPI2,	24,	0,	8},
-	{PERIPH_ID_SDMMC0,	0,	0,	8},
-	{PERIPH_ID_SDMMC1,	4,	16,	24},
-	{PERIPH_ID_SDMMC2,	8,	0,	8},
-	{PERIPH_ID_SDMMC3,	12,	16,	24},
-	{PERIPH_ID_I2S0,	0,	0,	4},
-	{PERIPH_ID_I2S1,	4,	12,	16},
-	{PERIPH_ID_SPI3,	0,	0,	4},
-	{PERIPH_ID_SPI4,	4,	12,	16},
-	{PERIPH_ID_SDMMC4,	16,	0,	8},
-	{PERIPH_ID_PWM0,	24,	0,	-1},
-	{PERIPH_ID_PWM1,	24,	0,	-1},
-	{PERIPH_ID_PWM2,	24,	0,	-1},
-	{PERIPH_ID_PWM3,	24,	0,	-1},
-	{PERIPH_ID_PWM4,	24,	0,	-1},
-
-	{PERIPH_ID_NONE,	-1,	-1,	-1},
+	/* periph id		s_mask	d_mask	p_mask	s_bit	d_bit	p_bit */
+	{PERIPH_ID_UART0,	0xf,	0xf,	-1,	0,	0,	-1},
+	{PERIPH_ID_UART1,	0xf,	0xf,	-1,	4,	4,	-1},
+	{PERIPH_ID_UART2,	0xf,	0xf,	-1,	8,	8,	-1},
+	{PERIPH_ID_UART3,	0xf,	0xf,	-1,	12,	12,	-1},
+	{PERIPH_ID_I2C0,	-1,	0x7,	0x7,	-1,	24,	0},
+	{PERIPH_ID_I2C1,	-1,	0x7,	0x7,	-1,	24,	0},
+	{PERIPH_ID_I2C2,	-1,	0x7,	0x7,	-1,	24,	0},
+	{PERIPH_ID_I2C3,	-1,	0x7,	0x7,	-1,	24,	0},
+	{PERIPH_ID_I2C4,	-1,	0x7,	0x7,	-1,	24,	0},
+	{PERIPH_ID_I2C5,	-1,	0x7,	0x7,	-1,	24,	0},
+	{PERIPH_ID_I2C6,	-1,	0x7,	0x7,	-1,	24,	0},
+	{PERIPH_ID_I2C7,	-1,	0x7,	0x7,	-1,	24,	0},
+	{PERIPH_ID_SPI0,	0xf,	0xf,	0xff,	16,	0,	8},
+	{PERIPH_ID_SPI1,	0xf,	0xf,	0xff,	20,	16,	24},
+	{PERIPH_ID_SPI2,	0xf,	0xf,	0xff,	24,	0,	8},
+	{PERIPH_ID_SDMMC0,	0xf,	0xf,	0xff,	0,	0,	8},
+	{PERIPH_ID_SDMMC1,	0xf,	0xf,	0xff,	4,	16,	24},
+	{PERIPH_ID_SDMMC2,	0xf,	0xf,	0xff,	8,	0,	8},
+	{PERIPH_ID_SDMMC3,	0xf,	0xf,	0xff,	12,	16,	24},
+	{PERIPH_ID_I2S0,	0xf,	0xf,	0xff,	0,	0,	4},
+	{PERIPH_ID_I2S1,	0xf,	0xf,	0xff,	4,	12,	16},
+	{PERIPH_ID_SPI3,	0xf,	0xf,	0xff,	0,	0,	4},
+	{PERIPH_ID_SPI4,	0xf,	0xf,	0xff,	4,	12,	16},
+	{PERIPH_ID_SDMMC4,	0xf,	0xf,	0xff,	16,	0,	8},
+	{PERIPH_ID_PWM0,	0xf,	0xf,	-1,	24,	0,	-1},
+	{PERIPH_ID_PWM1,	0xf,	0xf,	-1,	24,	0,	-1},
+	{PERIPH_ID_PWM2,	0xf,	0xf,	-1,	24,	0,	-1},
+	{PERIPH_ID_PWM3,	0xf,	0xf,	-1,	24,	0,	-1},
+	{PERIPH_ID_PWM4,	0xf,	0xf,	-1,	24,	0,	-1},
+
+	{PERIPH_ID_NONE,	-1,	-1,	-1,	-1,	-1,	-1},
 };
 
 static struct clk_bit_info exynos542x_bit_info[] = {
-	{PERIPH_ID_UART0,	4,	8,	-1},
-	{PERIPH_ID_UART1,	8,	12,	-1},
-	{PERIPH_ID_UART2,	12,	16,	-1},
-	{PERIPH_ID_UART3,	16,	20,	-1},
-	{PERIPH_ID_I2C0,	-1,	8,	-1},
-	{PERIPH_ID_I2C1,	-1,	8,	-1},
-	{PERIPH_ID_I2C2,	-1,	8,	-1},
-	{PERIPH_ID_I2C3,	-1,	8,	-1},
-	{PERIPH_ID_I2C4,	-1,	8,	-1},
-	{PERIPH_ID_I2C5,	-1,	8,	-1},
-	{PERIPH_ID_I2C6,	-1,	8,	-1},
-	{PERIPH_ID_I2C7,	-1,	8,	-1},
-	{PERIPH_ID_SPI0,	20,	20,	8},
-	{PERIPH_ID_SPI1,	24,	24,	16},
-	{PERIPH_ID_SPI2,	28,	28,	24},
-	{PERIPH_ID_SDMMC0,	8,	0,	-1},
-	{PERIPH_ID_SDMMC1,	12,	10,	-1},
-	{PERIPH_ID_SDMMC2,	16,	20,	-1},
-	{PERIPH_ID_I2C8,	-1,	8,	-1},
-	{PERIPH_ID_I2C9,	-1,	8,	-1},
-	{PERIPH_ID_I2S0,	0,	0,	4},
-	{PERIPH_ID_I2S1,	4,	12,	16},
-	{PERIPH_ID_SPI3,	12,	16,	0},
-	{PERIPH_ID_SPI4,	16,	20,	8},
-	{PERIPH_ID_PWM0,	24,	28,	-1},
-	{PERIPH_ID_PWM1,	24,	28,	-1},
-	{PERIPH_ID_PWM2,	24,	28,	-1},
-	{PERIPH_ID_PWM3,	24,	28,	-1},
-	{PERIPH_ID_PWM4,	24,	28,	-1},
-	{PERIPH_ID_I2C10,	-1,	8,	-1},
-
-	{PERIPH_ID_NONE,	-1,	-1,	-1},
+	/* periph id		s_mask	d_mask	p_mask	s_bit	d_bit	p_bit */
+	{PERIPH_ID_UART0,	0xf,	0xf,	-1,	4,	8,	-1},
+	{PERIPH_ID_UART1,	0xf,	0xf,	-1,	8,	12,	-1},
+	{PERIPH_ID_UART2,	0xf,	0xf,	-1,	12,	16,	-1},
+	{PERIPH_ID_UART3,	0xf,	0xf,	-1,	16,	20,	-1},
+	{PERIPH_ID_I2C0,	-1,	0x3f,	-1,	-1,	8,	-1},
+	{PERIPH_ID_I2C1,	-1,	0x3f,	-1,	-1,	8,	-1},
+	{PERIPH_ID_I2C2,	-1,	0x3f,	-1,	-1,	8,	-1},
+	{PERIPH_ID_I2C3,	-1,	0x3f,	-1,	-1,	8,	-1},
+	{PERIPH_ID_I2C4,	-1,	0x3f,	-1,	-1,	8,	-1},
+	{PERIPH_ID_I2C5,	-1,	0x3f,	-1,	-1,	8,	-1},
+	{PERIPH_ID_I2C6,	-1,	0x3f,	-1,	-1,	8,	-1},
+	{PERIPH_ID_I2C7,	-1,	0x3f,	-1,	-1,	8,	-1},
+	{PERIPH_ID_SPI0,	0xf,	0xf,	0xff,	20,	20,	8},
+	{PERIPH_ID_SPI1,	0xf,	0xf,	0xff,	24,	24,	16},
+	{PERIPH_ID_SPI2,	0xf,	0xf,	0xff,	28,	28,	24},
+	{PERIPH_ID_SDMMC0,	0x7,	0x3ff,	-1,	8,	0,	-1},
+	{PERIPH_ID_SDMMC1,	0x7,	0x3ff,	-1,	12,	10,	-1},
+	{PERIPH_ID_SDMMC2,	0x7,	0x3ff,	-1,	16,	20,	-1},
+	{PERIPH_ID_I2C8,	-1,	0x3f,	-1,	-1,	8,	-1},
+	{PERIPH_ID_I2C9,	-1,	0x3f,	-1,	-1,	8,	-1},
+	{PERIPH_ID_I2S0,	0xf,	0xf,	0xff,	0,	0,	4},
+	{PERIPH_ID_I2S1,	0xf,	0xf,	0xff,	4,	12,	16},
+	{PERIPH_ID_SPI3,	0xf,	0xf,	0xff,	12,	16,	0},
+	{PERIPH_ID_SPI4,	0xf,	0xf,	0xff,	16,	20,	8},
+	{PERIPH_ID_PWM0,	0xf,	0xf,	-1,	24,	28,	-1},
+	{PERIPH_ID_PWM1,	0xf,	0xf,	-1,	24,	28,	-1},
+	{PERIPH_ID_PWM2,	0xf,	0xf,	-1,	24,	28,	-1},
+	{PERIPH_ID_PWM3,	0xf,	0xf,	-1,	24,	28,	-1},
+	{PERIPH_ID_PWM4,	0xf,	0xf,	-1,	24,	28,	-1},
+	{PERIPH_ID_I2C10,	-1,	0x3f,	-1,	-1,	8,	-1},
+
+	{PERIPH_ID_NONE,	-1,	-1,	-1,	-1,	-1,	-1},
 };
 
 /* Epll Clock division values to achive different frequency output */
@@ -420,9 +424,9 @@ static unsigned long exynos5_get_periph_rate(int peripheral)
 	case PERIPH_ID_I2C7:
 		sclk = exynos5_get_pll_clk(MPLL);
 		sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit)
-								& 0x7) + 1;
+			    & bit_info->div_mask) + 1;
 		div = ((readl(&clk->div_top0) >> bit_info->prediv_bit)
-								& 0x7) + 1;
+			& bit_info->prediv_mask) + 1;
 		return (sclk / sub_div) / div;
 	default:
 		debug("%s: invalid peripheral %d", __func__, peripheral);
@@ -430,7 +434,7 @@ static unsigned long exynos5_get_periph_rate(int peripheral)
 	};
 
 	if (bit_info->src_bit >= 0)
-		src = (src >> bit_info->src_bit) & 0xf;
+		src = (src >> bit_info->src_bit) & bit_info->src_mask;
 
 	switch (src) {
 	case EXYNOS_SRC_MPLL:
@@ -448,12 +452,12 @@ static unsigned long exynos5_get_periph_rate(int peripheral)
 
 	/* Ratio clock division for this peripheral */
 	if (bit_info->div_bit >= 0) {
-		sub_div = (div >> bit_info->div_bit) & 0xf;
+		sub_div = (div >> bit_info->div_bit) & bit_info->div_mask;
 		sub_clk = sclk / (sub_div + 1);
 	}
 
 	if (bit_info->prediv_bit >= 0) {
-		div = (div >> bit_info->prediv_bit) & 0xff;
+		div = (div >> bit_info->prediv_bit) & bit_info->prediv_mask;
 		return sub_clk / (div + 1);
 	}
 
@@ -514,7 +518,7 @@ static unsigned long exynos542x_get_periph_rate(int peripheral)
 	case PERIPH_ID_I2C10:
 		sclk = exynos542x_get_pll_clk(MPLL);
 		sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit)
-								& 0x7) + 1;
+			    & bit_info->div_mask) + 1;
 		return sclk / sub_div;
 	default:
 		debug("%s: invalid peripheral %d", __func__, peripheral);
@@ -522,7 +526,7 @@ static unsigned long exynos542x_get_periph_rate(int peripheral)
 	};
 
 	if (bit_info->src_bit >= 0)
-		src = (src >> bit_info->src_bit) & 0xf;
+		src = (src >> bit_info->src_bit) & bit_info->src_mask;
 
 	switch (src) {
 	case EXYNOS542X_SRC_MPLL:
@@ -543,12 +547,13 @@ static unsigned long exynos542x_get_periph_rate(int peripheral)
 
 	/* Ratio clock division for this peripheral */
 	if (bit_info->div_bit >= 0) {
-		div = (div >> bit_info->div_bit) & 0xf;
+		div = (div >> bit_info->div_bit) & bit_info->div_mask;
 		sub_clk = sclk / (div + 1);
 	}
 
 	if (bit_info->prediv_bit >= 0) {
-		sub_div = (sub_div >> bit_info->prediv_bit) & 0xff;
+		sub_div = (sub_div >> bit_info->prediv_bit)
+						& bit_info->prediv_mask;
 		return sub_clk / (sub_div + 1);
 	}
 
-- 
1.9.1

[U-Boot] [PATCH v6 7/7] Exynos: Clock: Cleanup soc_get_periph_rate

[Akshay Saraswat]

Since we have src, div and pre-div mask bits defined corresponding
to peripherals, calculation of clock specific to I2C appears
redundant and confusing. Using clk_bit_info struct we can write
calculations generic to all peripherals which makes code easy to
understand and free from peripheral specific exceptions.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
---
Changes since v5:
	- Elaborated Commit message and fixed a nit.

Changes since v4:
	- New patch.

 arch/arm/cpu/armv7/exynos/clock.c | 74 ++++++++++++++++++---------------------
 1 file changed, 35 insertions(+), 39 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index 3884d4b..5777490 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -366,8 +366,8 @@ static struct clk_bit_info *get_clk_bit_info(int peripheral)
 static unsigned long exynos5_get_periph_rate(int peripheral)
 {
 	struct clk_bit_info *bit_info = get_clk_bit_info(peripheral);
-	unsigned long sclk, sub_clk = 0;
-	unsigned int src, div, sub_div = 0;
+	unsigned long sclk = 0;
+	unsigned int src = 0, div = 0, sub_div = 0;
 	struct exynos5_clock *clk =
 			(struct exynos5_clock *)samsung_get_base_clock();
 
@@ -389,30 +389,30 @@ static unsigned long exynos5_get_periph_rate(int peripheral)
 		break;
 	case PERIPH_ID_I2S0:
 		src = readl(&clk->src_mau);
-		div = readl(&clk->div_mau);
+		div = sub_div = readl(&clk->div_mau);
 	case PERIPH_ID_SPI0:
 	case PERIPH_ID_SPI1:
 		src = readl(&clk->src_peric1);
-		div = readl(&clk->div_peric1);
+		div = sub_div = readl(&clk->div_peric1);
 		break;
 	case PERIPH_ID_SPI2:
 		src = readl(&clk->src_peric1);
-		div = readl(&clk->div_peric2);
+		div = sub_div = readl(&clk->div_peric2);
 		break;
 	case PERIPH_ID_SPI3:
 	case PERIPH_ID_SPI4:
 		src = readl(&clk->sclk_src_isp);
-		div = readl(&clk->sclk_div_isp);
+		div = sub_div = readl(&clk->sclk_div_isp);
 		break;
 	case PERIPH_ID_SDMMC0:
 	case PERIPH_ID_SDMMC1:
 		src = readl(&clk->src_fsys);
-		div = readl(&clk->div_fsys1);
+		div = sub_div = readl(&clk->div_fsys1);
 		break;
 	case PERIPH_ID_SDMMC2:
 	case PERIPH_ID_SDMMC3:
 		src = readl(&clk->src_fsys);
-		div = readl(&clk->div_fsys2);
+		div = sub_div = readl(&clk->div_fsys2);
 		break;
 	case PERIPH_ID_I2C0:
 	case PERIPH_ID_I2C1:
@@ -422,12 +422,10 @@ static unsigned long exynos5_get_periph_rate(int peripheral)
 	case PERIPH_ID_I2C5:
 	case PERIPH_ID_I2C6:
 	case PERIPH_ID_I2C7:
-		sclk = exynos5_get_pll_clk(MPLL);
-		sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit)
-			    & bit_info->div_mask) + 1;
-		div = ((readl(&clk->div_top0) >> bit_info->prediv_bit)
-			& bit_info->prediv_mask) + 1;
-		return (sclk / sub_div) / div;
+		src = EXYNOS_SRC_MPLL;
+		div = readl(&clk->div_top0);
+		sub_div = readl(&clk->div_top1);
+		break;
 	default:
 		debug("%s: invalid peripheral %d", __func__, peripheral);
 		return -1;
@@ -447,28 +445,28 @@ static unsigned long exynos5_get_periph_rate(int peripheral)
 		sclk = exynos5_get_pll_clk(VPLL);
 		break;
 	default:
+		debug("%s: EXYNOS_SRC %d not supported\n", __func__, src);
 		return 0;
 	}
 
-	/* Ratio clock division for this peripheral */
-	if (bit_info->div_bit >= 0) {
-		sub_div = (div >> bit_info->div_bit) & bit_info->div_mask;
-		sub_clk = sclk / (sub_div + 1);
-	}
+	/* Clock divider ratio for this peripheral */
+	if (bit_info->div_bit >= 0)
+		div = (div >> bit_info->div_bit) & bit_info->div_mask;
 
-	if (bit_info->prediv_bit >= 0) {
-		div = (div >> bit_info->prediv_bit) & bit_info->prediv_mask;
-		return sub_clk / (div + 1);
-	}
+	/* Clock pre-divider ratio for this peripheral */
+	if (bit_info->prediv_bit >= 0)
+		sub_div = (sub_div >> bit_info->prediv_bit)
+			  & bit_info->prediv_mask;
 
-	return sub_clk;
+	/* Calculate and return required clock rate */
+	return (sclk / (div + 1)) / (sub_div + 1);
 }
 
 static unsigned long exynos542x_get_periph_rate(int peripheral)
 {
 	struct clk_bit_info *bit_info = get_clk_bit_info(peripheral);
-	unsigned long sclk, sub_clk = 0;
-	unsigned int src, div, sub_div = 0;
+	unsigned long sclk = 0;
+	unsigned int src = 0, div = 0, sub_div = 0;
 	struct exynos5420_clock *clk =
 			(struct exynos5420_clock *)samsung_get_base_clock();
 
@@ -516,10 +514,9 @@ static unsigned long exynos542x_get_periph_rate(int peripheral)
 	case PERIPH_ID_I2C8:
 	case PERIPH_ID_I2C9:
 	case PERIPH_ID_I2C10:
-		sclk = exynos542x_get_pll_clk(MPLL);
-		sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit)
-			    & bit_info->div_mask) + 1;
-		return sclk / sub_div;
+		src = EXYNOS542X_SRC_MPLL;
+		div = readl(&clk->div_top1);
+		break;
 	default:
 		debug("%s: invalid peripheral %d", __func__, peripheral);
 		return -1;
@@ -542,22 +539,21 @@ static unsigned long exynos542x_get_periph_rate(int peripheral)
 		sclk = exynos542x_get_pll_clk(RPLL);
 		break;
 	default:
+		debug("%s: EXYNOS542X_SRC %d not supported", __func__, src);
 		return 0;
 	}
 
-	/* Ratio clock division for this peripheral */
-	if (bit_info->div_bit >= 0) {
+	/* Clock divider ratio for this peripheral */
+	if (bit_info->div_bit >= 0)
 		div = (div >> bit_info->div_bit) & bit_info->div_mask;
-		sub_clk = sclk / (div + 1);
-	}
 
-	if (bit_info->prediv_bit >= 0) {
+	/* Clock pre-divider ratio for this peripheral */
+	if (bit_info->prediv_bit >= 0)
 		sub_div = (sub_div >> bit_info->prediv_bit)
-						& bit_info->prediv_mask;
-		return sub_clk / (sub_div + 1);
-	}
+			  & bit_info->prediv_mask;
 
-	return sub_clk;
+	/* Calculate and return required clock rate */
+	return (sclk / (div + 1)) / (sub_div + 1);
 }
 
 unsigned long clock_get_periph_rate(int peripheral)
-- 
1.9.1

[U-Boot] [PATCH v6 7/7] Exynos: Clock: Cleanup soc_get_periph_rate

[Joonyoung Shim]

Hi Akshay,

On 02/04/2015 07:30 PM, Akshay Saraswat wrote:
> Since we have src, div and pre-div mask bits defined corresponding
> to peripherals, calculation of clock specific to I2C appears
> redundant and confusing. Using clk_bit_info struct we can write
> calculations generic to all peripherals which makes code easy to
> understand and free from peripheral specific exceptions.
> 
> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
> ---
> Changes since v5:
> 	- Elaborated Commit message and fixed a nit.
> 
> Changes since v4:
> 	- New patch.
> 
>  arch/arm/cpu/armv7/exynos/clock.c | 74 ++++++++++++++++++---------------------
>  1 file changed, 35 insertions(+), 39 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
> index 3884d4b..5777490 100644
> --- a/arch/arm/cpu/armv7/exynos/clock.c
> +++ b/arch/arm/cpu/armv7/exynos/clock.c
> @@ -366,8 +366,8 @@ static struct clk_bit_info *get_clk_bit_info(int peripheral)
>  static unsigned long exynos5_get_periph_rate(int peripheral)
>  {
>  	struct clk_bit_info *bit_info = get_clk_bit_info(peripheral);
> -	unsigned long sclk, sub_clk = 0;
> -	unsigned int src, div, sub_div = 0;
> +	unsigned long sclk = 0;
> +	unsigned int src = 0, div = 0, sub_div = 0;
>  	struct exynos5_clock *clk =
>  			(struct exynos5_clock *)samsung_get_base_clock();
>  
> @@ -389,30 +389,30 @@ static unsigned long exynos5_get_periph_rate(int peripheral)
>  		break;
>  	case PERIPH_ID_I2S0:
>  		src = readl(&clk->src_mau);
> -		div = readl(&clk->div_mau);
> +		div = sub_div = readl(&clk->div_mau);

I just do scripts/checkpatch.pl and get follow results.

CHECK: multiple assignments should be avoided
#37: FILE: arch/arm/cpu/armv7/exynos/clock.c:392:
+		div = sub_div = readl(&clk->div_mau);

CHECK: multiple assignments should be avoided
#42: FILE: arch/arm/cpu/armv7/exynos/clock.c:396:
+		div = sub_div = readl(&clk->div_peric1);

CHECK: multiple assignments should be avoided
#47: FILE: arch/arm/cpu/armv7/exynos/clock.c:400:
+		div = sub_div = readl(&clk->div_peric2);

CHECK: multiple assignments should be avoided
#53: FILE: arch/arm/cpu/armv7/exynos/clock.c:405:
+		div = sub_div = readl(&clk->sclk_div_isp);

CHECK: multiple assignments should be avoided
#59: FILE: arch/arm/cpu/armv7/exynos/clock.c:410:
+		div = sub_div = readl(&clk->div_fsys1);

CHECK: multiple assignments should be avoided
#65: FILE: arch/arm/cpu/armv7/exynos/clock.c:415:
+		div = sub_div = readl(&clk->div_fsys2);

total: 0 errors, 0 warnings, 6 checks, 145 lines checked

Thanks.

>  	case PERIPH_ID_SPI0:
>  	case PERIPH_ID_SPI1:
>  		src = readl(&clk->src_peric1);
> -		div = readl(&clk->div_peric1);
> +		div = sub_div = readl(&clk->div_peric1);
>  		break;
>  	case PERIPH_ID_SPI2:
>  		src = readl(&clk->src_peric1);
> -		div = readl(&clk->div_peric2);
> +		div = sub_div = readl(&clk->div_peric2);
>  		break;
>  	case PERIPH_ID_SPI3:
>  	case PERIPH_ID_SPI4:
>  		src = readl(&clk->sclk_src_isp);
> -		div = readl(&clk->sclk_div_isp);
> +		div = sub_div = readl(&clk->sclk_div_isp);
>  		break;
>  	case PERIPH_ID_SDMMC0:
>  	case PERIPH_ID_SDMMC1:
>  		src = readl(&clk->src_fsys);
> -		div = readl(&clk->div_fsys1);
> +		div = sub_div = readl(&clk->div_fsys1);
>  		break;
>  	case PERIPH_ID_SDMMC2:
>  	case PERIPH_ID_SDMMC3:
>  		src = readl(&clk->src_fsys);
> -		div = readl(&clk->div_fsys2);
> +		div = sub_div = readl(&clk->div_fsys2);
>  		break;
>  	case PERIPH_ID_I2C0:
>  	case PERIPH_ID_I2C1:
> @@ -422,12 +422,10 @@ static unsigned long exynos5_get_periph_rate(int peripheral)
>  	case PERIPH_ID_I2C5:
>  	case PERIPH_ID_I2C6:
>  	case PERIPH_ID_I2C7:
> -		sclk = exynos5_get_pll_clk(MPLL);
> -		sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit)
> -			    & bit_info->div_mask) + 1;
> -		div = ((readl(&clk->div_top0) >> bit_info->prediv_bit)
> -			& bit_info->prediv_mask) + 1;
> -		return (sclk / sub_div) / div;
> +		src = EXYNOS_SRC_MPLL;
> +		div = readl(&clk->div_top0);
> +		sub_div = readl(&clk->div_top1);
> +		break;
>  	default:
>  		debug("%s: invalid peripheral %d", __func__, peripheral);
>  		return -1;
> @@ -447,28 +445,28 @@ static unsigned long exynos5_get_periph_rate(int peripheral)
>  		sclk = exynos5_get_pll_clk(VPLL);
>  		break;
>  	default:
> +		debug("%s: EXYNOS_SRC %d not supported\n", __func__, src);
>  		return 0;
>  	}
>  
> -	/* Ratio clock division for this peripheral */
> -	if (bit_info->div_bit >= 0) {
> -		sub_div = (div >> bit_info->div_bit) & bit_info->div_mask;
> -		sub_clk = sclk / (sub_div + 1);
> -	}
> +	/* Clock divider ratio for this peripheral */
> +	if (bit_info->div_bit >= 0)
> +		div = (div >> bit_info->div_bit) & bit_info->div_mask;
>  
> -	if (bit_info->prediv_bit >= 0) {
> -		div = (div >> bit_info->prediv_bit) & bit_info->prediv_mask;
> -		return sub_clk / (div + 1);
> -	}
> +	/* Clock pre-divider ratio for this peripheral */
> +	if (bit_info->prediv_bit >= 0)
> +		sub_div = (sub_div >> bit_info->prediv_bit)
> +			  & bit_info->prediv_mask;
>  
> -	return sub_clk;
> +	/* Calculate and return required clock rate */
> +	return (sclk / (div + 1)) / (sub_div + 1);
>  }
>  
>  static unsigned long exynos542x_get_periph_rate(int peripheral)
>  {
>  	struct clk_bit_info *bit_info = get_clk_bit_info(peripheral);
> -	unsigned long sclk, sub_clk = 0;
> -	unsigned int src, div, sub_div = 0;
> +	unsigned long sclk = 0;
> +	unsigned int src = 0, div = 0, sub_div = 0;
>  	struct exynos5420_clock *clk =
>  			(struct exynos5420_clock *)samsung_get_base_clock();
>  
> @@ -516,10 +514,9 @@ static unsigned long exynos542x_get_periph_rate(int peripheral)
>  	case PERIPH_ID_I2C8:
>  	case PERIPH_ID_I2C9:
>  	case PERIPH_ID_I2C10:
> -		sclk = exynos542x_get_pll_clk(MPLL);
> -		sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit)
> -			    & bit_info->div_mask) + 1;
> -		return sclk / sub_div;
> +		src = EXYNOS542X_SRC_MPLL;
> +		div = readl(&clk->div_top1);
> +		break;
>  	default:
>  		debug("%s: invalid peripheral %d", __func__, peripheral);
>  		return -1;
> @@ -542,22 +539,21 @@ static unsigned long exynos542x_get_periph_rate(int peripheral)
>  		sclk = exynos542x_get_pll_clk(RPLL);
>  		break;
>  	default:
> +		debug("%s: EXYNOS542X_SRC %d not supported", __func__, src);
>  		return 0;
>  	}
>  
> -	/* Ratio clock division for this peripheral */
> -	if (bit_info->div_bit >= 0) {
> +	/* Clock divider ratio for this peripheral */
> +	if (bit_info->div_bit >= 0)
>  		div = (div >> bit_info->div_bit) & bit_info->div_mask;
> -		sub_clk = sclk / (div + 1);
> -	}
>  
> -	if (bit_info->prediv_bit >= 0) {
> +	/* Clock pre-divider ratio for this peripheral */
> +	if (bit_info->prediv_bit >= 0)
>  		sub_div = (sub_div >> bit_info->prediv_bit)
> -						& bit_info->prediv_mask;
> -		return sub_clk / (sub_div + 1);
> -	}
> +			  & bit_info->prediv_mask;
>  
> -	return sub_clk;
> +	/* Calculate and return required clock rate */
> +	return (sclk / (div + 1)) / (sub_div + 1);
>  }
>  
>  unsigned long clock_get_periph_rate(int peripheral)
> 

[U-Boot] [PATCH v6 0/7] Exynos5: Fix warnings and enrich clock_get_periph_rate

[Joonyoung Shim]

Hi Akshay,

On 02/04/2015 07:29 PM, Akshay Saraswat wrote:
> This patch series does following changes -
> 1. Removing compiler warnings for clock_get_periph_rate.
> 2. Adding and enabling support for Exynos542x in
>    clock_get_periph_rate.
> 3. Replacing peripheral specific function calls with
>    clock_get_periph_rate.
> 4. Remove code from clocks file which became useless due to
>    introduction of clock_get_periph_rate.
> 
> Changes since v5:
> 	- Elaborated commit message and fixed a nit.
> 
> Changes since v4:
> 	- Added Reviewed-by in patches 3 and 5.
> 	- Split patch 6 of version 4 into two patches 6 and 7.
> 
> Changes since v3:
> 	- Added Reviewed-by & Tested-by in patches 1, 2 and 4.
> 	- Patch-3: Handled SPLL case in exynos542x_get_periph_rate.
> 	- Patch-3: Changed EXYNOS542x -> EXYNOS542X in pll_src_bit enum.
> 	- Merged pathces 5 and 6 of version 3.
> 	- Patch-6: New patch for dealing with variety of mask bits.
> 
> Changes since v2:
> 	- Patch-1: Added debug message for unknown periph IDs.
> 	- Patch-2: Changed exynos5420 -> exynos542x in comment.
> 	- Patch-3: Fixed enum and soc_get_periph_rate switch.
> 	- Patch-3: Added checks for negative values in soc_get_periph_rate.
> 	- Patch-4: Added checks for negative values in soc_get_periph_rate.
> 
> Changes since v1:
> 	- Added 2 new patches.
> 
> 
> Akshay Saraswat (7):
>   Exynos5: Fix compiler warnings due to clock_get_periph_rate
>   Exynos542x: Move exynos5420_get_pll_clk up and rename
>   Exynos542x: Add and enable get_periph_rate support
>   Exynos5: Fix exynos5_get_periph_rate calculations
>   Exynos5: Use clock_get_periph_rate generic API
>   Exynos: clock: change mask bits as per peripheral
>   Exynos: Clock: Cleanup soc_get_periph_rate
> 
>  arch/arm/cpu/armv7/exynos/clock.c      | 617 ++++++++++++++++-----------------
>  arch/arm/include/asm/arch-exynos/clk.h |   4 +
>  2 files changed, 298 insertions(+), 323 deletions(-)
> 

This v6 is fine to me even if there are style problems of checkpatch.pl
from 7/7 patch.

Acked-by: Joonyoung Shim <jy0922.shim@samsung.com>

Thanks.

[U-Boot] [PATCH v6 0/7] Exynos5: Fix warnings and enrich clock_get_periph_rate

[Minkyu Kang]

On 04/02/15 19:29, Akshay Saraswat wrote:
> This patch series does following changes -
> 1. Removing compiler warnings for clock_get_periph_rate.
> 2. Adding and enabling support for Exynos542x in
>    clock_get_periph_rate.
> 3. Replacing peripheral specific function calls with
>    clock_get_periph_rate.
> 4. Remove code from clocks file which became useless due to
>    introduction of clock_get_periph_rate.
> 
> Changes since v5:
> 	- Elaborated commit message and fixed a nit.
> 
> Changes since v4:
> 	- Added Reviewed-by in patches 3 and 5.
> 	- Split patch 6 of version 4 into two patches 6 and 7.
> 
> Changes since v3:
> 	- Added Reviewed-by & Tested-by in patches 1, 2 and 4.
> 	- Patch-3: Handled SPLL case in exynos542x_get_periph_rate.
> 	- Patch-3: Changed EXYNOS542x -> EXYNOS542X in pll_src_bit enum.
> 	- Merged pathces 5 and 6 of version 3.
> 	- Patch-6: New patch for dealing with variety of mask bits.
> 
> Changes since v2:
> 	- Patch-1: Added debug message for unknown periph IDs.
> 	- Patch-2: Changed exynos5420 -> exynos542x in comment.
> 	- Patch-3: Fixed enum and soc_get_periph_rate switch.
> 	- Patch-3: Added checks for negative values in soc_get_periph_rate.
> 	- Patch-4: Added checks for negative values in soc_get_periph_rate.
> 
> Changes since v1:
> 	- Added 2 new patches.
> 
> 
> Akshay Saraswat (7):
>   Exynos5: Fix compiler warnings due to clock_get_periph_rate
>   Exynos542x: Move exynos5420_get_pll_clk up and rename
>   Exynos542x: Add and enable get_periph_rate support
>   Exynos5: Fix exynos5_get_periph_rate calculations
>   Exynos5: Use clock_get_periph_rate generic API
>   Exynos: clock: change mask bits as per peripheral
>   Exynos: Clock: Cleanup soc_get_periph_rate
> 
>  arch/arm/cpu/armv7/exynos/clock.c      | 617 ++++++++++++++++-----------------
>  arch/arm/include/asm/arch-exynos/clk.h |   4 +
>  2 files changed, 298 insertions(+), 323 deletions(-)
> 

applied to u-boot-samsung.

Thank,
Minkyu Kang.