From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefano Babic Date: Tue, 10 Feb 2015 11:22:17 +0100 Subject: [U-Boot] [PATCH 2/4] mx6: soc: Add ENET2 support In-Reply-To: <1421052378-29913-2-git-send-email-B37916@freescale.com> References: <1421052378-29913-1-git-send-email-B37916@freescale.com> <1421052378-29913-2-git-send-email-B37916@freescale.com> Message-ID: <54D9DBD9.70009@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi, On 12/01/2015 09:46, Ye.Li wrote: > The mx6sx has two ENET controllers, some board like mx6sxsabreauto > uses the ENET2 for ethernet. So add ENET2 support to soc level, > including: ENET2 clock enable and MAC address fuse for ENET2. > > Signed-off-by: Ye.Li > --- > arch/arm/cpu/armv7/mx6/clock.c | 9 ++++++++- > arch/arm/cpu/armv7/mx6/soc.c | 25 ++++++++++++++++++++++++- > arch/arm/include/asm/arch-mx6/crm_regs.h | 7 +++++++ > 3 files changed, 39 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c > index 055f44e..fd57f22 100644 > --- a/arch/arm/cpu/armv7/mx6/clock.c > +++ b/arch/arm/cpu/armv7/mx6/clock.c > @@ -498,7 +498,11 @@ int enable_fec_anatop_clock(enum enet_freq freq) > > reg = readl(&anatop->pll_enet); > reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT; > - reg |= freq; > + reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq); > +#ifdef CONFIG_MX6SX > + reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT; > + reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq); > +#endif > > if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) || > (!(reg & BM_ANADIG_PLL_ENET_LOCK))) { > @@ -514,6 +518,9 @@ int enable_fec_anatop_clock(enum enet_freq freq) > > /* Enable FEC clock */ > reg |= BM_ANADIG_PLL_ENET_ENABLE; > +#ifdef CONFIG_MX6SX > + reg |= BM_ANADIG_PLL_ENET2_ENABLE; > +#endif > reg &= ~BM_ANADIG_PLL_ENET_BYPASS; > writel(reg, &anatop->pll_enet); > > diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c > index 5f5f497..4994eab 100644 > --- a/arch/arm/cpu/armv7/mx6/soc.c > +++ b/arch/arm/cpu/armv7/mx6/soc.c > @@ -337,6 +337,29 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) > struct fuse_bank4_regs *fuse = > (struct fuse_bank4_regs *)bank->fuse_regs; > > +#ifdef CONFIG_MX6SX > + if (0 == dev_id) { > + u32 value = readl(&fuse->mac_addr_high); > + mac[0] = (value >> 8); > + mac[1] = value ; > + > + value = readl(&fuse->mac_addr_low); > + mac[2] = value >> 24 ; ^--- Checkpatch complains about extra spaces. > + mac[3] = value >> 16 ; > + mac[4] = value >> 8 ; > + mac[5] = value ; > + } else { > + u32 value = readl(&fuse->mac_addr2); > + mac[0] = value >> 24 ; > + mac[1] = value >> 16 ; > + mac[2] = value >> 8 ; > + mac[3] = value ; > + > + value = readl(&fuse->mac_addr_high); > + mac[4] = value >> 24 ; > + mac[5] = value >> 16 ; Is it desired that the layout is different between the two mac addresses ? As far as I know, MAC_ADDR in fuses is reserved to customers, and it makes sense they have the same layout. Is there some reason (that I do not know, obviously) to have them different ? > + } > +#else > u32 value = readl(&fuse->mac_addr_high); > mac[0] = (value >> 8); > mac[1] = value ; > @@ -346,7 +369,7 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) > mac[3] = value >> 16 ; > mac[4] = value >> 8 ; > mac[5] = value ; > - > +#endif > } > #endif > > diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h > index 39f3c07..eec03cf 100644 > --- a/arch/arm/include/asm/arch-mx6/crm_regs.h > +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h > @@ -1012,6 +1012,13 @@ struct mxc_ccm_reg { > #define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003 > #define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \ > (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT) > +#ifdef CONFIG_MX6SX > +#define BM_ANADIG_PLL_ENET2_ENABLE 0x00100000 > + > +#define BM_ANADIG_PLL_ENET2_DIV_SELECT 0x0000000C > +#define BF_ANADIG_PLL_ENET2_DIV_SELECT(v) \ > + (((v) << 2) & BM_ANADIG_PLL_ENET2_DIV_SELECT) > +#endif > > #define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000 > #define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000 > Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de =====================================================================