public inbox for u-boot@lists.denx.de
 help / color / mirror / Atom feed
From: Li Ye-B37916 <b37916@freescale.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 3/4] mx6: clock: Modify GPMI clock to support mx6sx
Date: Wed, 11 Feb 2015 11:14:07 +0800	[thread overview]
Message-ID: <54DAC8FF.4030203@freescale.com> (raw)
In-Reply-To: <54D9DCE0.4040800@denx.de>

Hi Stefano,

On 2/10/2015 6:26 PM, Stefano Babic wrote:
> Hi Ye,
>
> On 12/01/2015 09:46, Ye.Li wrote:
>> On mx6sx, the CCM register bits for GPMI are different as other
>> mx6 platforms. Modify the GPMI clock function to support mx6sx.
>>
>> Signed-off-by: Ye.Li <B37916@freescale.com>
>> ---
>>  arch/arm/cpu/armv7/mx6/clock.c |   12 ++++++++++++
>>  1 files changed, 12 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
>> index fd57f22..ce7f0f7 100644
>> --- a/arch/arm/cpu/armv7/mx6/clock.c
>> +++ b/arch/arm/cpu/armv7/mx6/clock.c
>> @@ -47,6 +47,17 @@ void setup_gpmi_io_clk(u32 cfg)
>>  		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
>>  		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
>>  
>> +#if defined(CONFIG_MX6SX)
>> +	clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
>> +
>> +	clrsetbits_le32(&imx_ccm->cs2cdr,
>> +			MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
>> +			MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
>> +			MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK,
>> +			cfg);
>> +
>> +	setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
>> +#els
> If I have well understood, this code is protected by CONFIG_NAND_MXS,
> and that conflicts with what you are willing to do (setting clocks for
> QSPI). I suggest to split setup_gpmi_io_clk() function, that at the
> moment is ony for NAND, having something like:
>
> void setup_gpmi_io_clk()
> {
> #ifdef CONFIG_NAND_MXS
>
> 	...setup nand
> #endif
>
> 	...setup qspi
>
> }
>
> Best regards,
> Stefano Babic
>
I feel you misunderstand the patch. On i.MX6sx, the QSPI2 and GPMI shares the same clock root of QSPI2. So you can see the register bits are
named with "MXC_CCM_CS2CDR_QSPI2_xxx". Actually, not only the name, there is a little different in the CS2CDR register bits layout.  The patch is used to fix the gap. 

Also the the GPMI pins are multiplexed with QSPI2 pins, so either NAND or QSPI2 can work,  there is no conflict.

Best regards,
Ye Li

  reply	other threads:[~2015-02-11  3:14 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-01-12  8:46 [U-Boot] [PATCH 1/4] mx6sx: pins: Enable SION for I2C3 iomux setting Ye.Li
2015-01-12  8:46 ` [U-Boot] [PATCH 2/4] mx6: soc: Add ENET2 support Ye.Li
2015-02-10 10:22   ` Stefano Babic
2015-02-11  2:42     ` Li Ye-B37916
2015-02-11 12:46       ` Stefano Babic
2015-01-12  8:46 ` [U-Boot] [PATCH 3/4] mx6: clock: Modify GPMI clock to support mx6sx Ye.Li
2015-02-10 10:26   ` Stefano Babic
2015-02-11  3:14     ` Li Ye-B37916 [this message]
2015-02-11 12:48       ` Stefano Babic
2015-01-12  8:46 ` [U-Boot] [PATCH 4/4] imx: mx6sxsabreauto: Add support for mx6sx SABREAUTO board Ye.Li
2015-02-10 10:51   ` Stefano Babic
2015-02-11  9:43     ` Li Ye-B37916
2015-02-11 13:21       ` Peng Fan
2015-01-12 10:37 ` [U-Boot] [PATCH 1/4] mx6sx: pins: Enable SION for I2C3 iomux setting Nikolay Dimitrov
2015-01-29 17:54   ` Stefano Babic
2015-02-09 13:27     ` Li Ye-B37916
2015-02-10 10:18       ` Stefano Babic
2015-02-15 15:11         ` Nikolay Dimitrov
2015-02-15 16:23           ` Stefano Babic
  -- strict thread matches above, loose matches on Subject: below --
2015-11-24 14:38 [U-Boot] [PATCH 3/4] mx6: clock: Modify GPMI clock to support mx6sx Bärtsch Peter
2015-11-25 10:40 ` Stefano Babic

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=54DAC8FF.4030203@freescale.com \
    --to=b37916@freescale.com \
    --cc=u-boot@lists.denx.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox