[U-Boot] [PATCH 1/4] mx6sx: pins: Enable SION for I2C3 iomux setting

Nikolay Dimitrov
2015-02-15T15:11:23Z

Hi guys,

On 02/10/2015 12:18 PM, Stefano Babic wrote:
> Hi,
>
> On 09/02/2015 14:27, Li Ye-B37916 wrote:
>> Hi Stefano, Nikolay,
>>
>> On 1/30/2015 1:54 AM, Stefano Babic wrote:
>>> Hi,
>>>
>>> On 12/01/2015 11:37, Nikolay Dimitrov wrote:
>>>> Hi Ye.Li,
>>>>
>>>> On 01/12/2015 10:46 AM, Ye.Li wrote:
>>>>> The I2C SDA and SCL require the IOMUX SION bit set to get input signal.
>>>>>
>>>>> Signed-off-by: Ye.Li <B37916@freescale.com>
>>>>> ---
>>>>> arch/arm/include/asm/arch-mx6/mx6sx_pins.h | 4 ++--
>>>>> 1 files changed, 2 insertions(+), 2 deletions(-)
>>>>>
>>>>> diff --git a/arch/arm/include/asm/arch-mx6/mx6sx_pins.h
>>>>> b/arch/arm/include/asm/arch-mx6/mx6sx_pins.h
>>>>> index 7c6c1e8..da8c698 100644
>>>>> --- a/arch/arm/include/asm/arch-mx6/mx6sx_pins.h
>>>>> +++ b/arch/arm/include/asm/arch-mx6/mx6sx_pins.h
>>>>> @@ -420,7 +420,7 @@ enum {
>>>>>
>>>>> MX6_PAD_KEY_COL4__KPP_COL_4 =
>>>>> IOMUX_PAD(0x03FC, 0x00B4, 0, 0x0000, 0, 0),
>>>>> MX6_PAD_KEY_COL4__ENET2_MDC =
>>>>> IOMUX_PAD(0x03FC, 0x00B4, 1, 0x0000, 0, 0),
>>>>> - MX6_PAD_KEY_COL4__I2C3_SCL =
>>>>> IOMUX_PAD(0x03FC, 0x00B4, 2, 0x07B8, 2, 0),
>>>>> + MX6_PAD_KEY_COL4__I2C3_SCL =
>>>>> IOMUX_PAD(0x03FC, 0x00B4, IOMUX_CONFIG_SION | 2, 0x07B8, 2, 0),
>>>>> MX6_PAD_KEY_COL4__USDHC2_LCTL =
>>>>> IOMUX_PAD(0x03FC, 0x00B4, 3, 0x0000, 0, 0),
>>>>> MX6_PAD_KEY_COL4__AUDMUX_AUD5_RXC =
>>>>> IOMUX_PAD(0x03FC, 0x00B4, 4, 0x0664, 0, 0),
>>>>> MX6_PAD_KEY_COL4__GPIO2_IO_14 =
>>>>> IOMUX_PAD(0x03FC, 0x00B4, 5, 0x0000, 0, 0),
>>>>> @@ -467,7 +467,7 @@ enum {
>>>>>
>>>>> MX6_PAD_KEY_ROW4__KPP_ROW_4 =
>>>>> IOMUX_PAD(0x0410, 0x00C8, 0, 0x0000, 0, 0),
>>>>> MX6_PAD_KEY_ROW4__ENET2_MDIO =
>>>>> IOMUX_PAD(0x0410, 0x00C8, 1, 0x0770, 3, 0),
>>>>> - MX6_PAD_KEY_ROW4__I2C3_SDA =
>>>>> IOMUX_PAD(0x0410, 0x00C8, 2, 0x07BC, 2, 0),
>>>>> + MX6_PAD_KEY_ROW4__I2C3_SDA =
>>>>> IOMUX_PAD(0x0410, 0x00C8, IOMUX_CONFIG_SION | 2, 0x07BC, 2, 0),
>>>>> MX6_PAD_KEY_ROW4__USDHC1_LCTL =
>>>>> IOMUX_PAD(0x0410, 0x00C8, 3, 0x0000, 0, 0),
>>>>> MX6_PAD_KEY_ROW4__AUDMUX_AUD5_RXFS =
>>>>> IOMUX_PAD(0x0410, 0x00C8, 4, 0x0668, 0, 0),
>>>>> MX6_PAD_KEY_ROW4__GPIO2_IO_19 =
>>>>> IOMUX_PAD(0x0410, 0x00C8, 5, 0x0000, 0, 0),
>>>>>
>>>> Usually the SCL is output-only, driven by the I2C master. Why do you
>>>> need to enable SION bit on SCL, if the pin will be used as output-only?
>>>>
>>> Right - I do not see why SION should be set.
>>>
>>> Regards,
>>> Stefano Babic
>>>
>>
>> Setting SION to both SDA and SCL is required by i.MX6 reference manual. You can find the information below from i2c chapter.
>>
>> 34.2 External Signals
>> This section discusses I2C signals that connect off-chip.
>> For I2C compliance, all devices connected to the I2Cn_SCL and I2Cn_SDA signals must
>> have open-drain or open-collector outputs. The logic AND function is implemented on
>> both lines with external pull-up resistors.
>> Inputs of I2Cn_SCL and I2Cn_SDA also need to be manually enabled by setting the
>> SION bit in the IOMUX after the corresponding PADs are selected as I2C function.
>>
>
> Checked in manual, thanks for link. However, I have still a couple of
> questions. The controller can work as slave or as master, and according
> to the manual, the slave is the default after a reset. I understand that
> putting the controller into slave mode must require the SION bit set.
> Anyway, you are using I2C3 as master in your patch 4/4. Is it still
> mandatory even in this case to set the SION bit ? The manual states that
> to use the signal as input the SION bit must be set, but as far as I see
> in the patchset SCL is output only.

Just tested the behavior of SION bit on imx6sl (riotboard), as I don't
have imx6sx hardware.

For the test I used I2C4, located on expansion connector J13. I
verified that the SION bits are enabled after boot:

# devregs IOMUXC_SW_MUX_CTL_PAD_GPIO07
IOMUXC_SW_MUX_CTL_PAD_GPIO07:0x020e0238 =0x00000018

# devregs IOMUXC_SW_MUX_CTL_PAD_GPIO08
IOMUXC_SW_MUX_CTL_PAD_GPIO08:0x020e023c =0x00000018

I also verified that the I2C interface works as expected (by observing
I2C transactions on a digital scope):

i2cdetect -y 3

This works so far. Then I disabled the SION bits for both iomuxes:

# devregs IOMUXC_SW_MUX_CTL_PAD_GPIO07 0x08
IOMUXC_SW_MUX_CTL_PAD_GPIO07:0x020e0238 =0x00000018
IOMUXC_SW_MUX_CTL_PAD_GPIO07:0x020e0238 == 0x00000018...0x00000008

# devregs IOMUXC_SW_MUX_CTL_PAD_GPIO08 0x08
IOMUXC_SW_MUX_CTL_PAD_GPIO08:0x020e023c =0x00000018
IOMUXC_SW_MUX_CTL_PAD_GPIO08:0x020e023c == 0x00000018...0x00000008

Now interface I2C4 doesn't work anymore. Instead of complete I2C
transactions, I see just a single pulses on both clock/data lines,
repeated on each 500ms. At the same time i2cdetect scans the address
space much more slowly than usual, and it looks like it timeouts on
each single address check for the same amount of time (500ms).

Restoring the SION bits for clock & data restores the I2C4
functionality. All the time the port was in master mode.

I don't have experience with imx6sx, but if the I2C IP core was reused
for imx6sx (which is very likely), then I tend to agree with Ye Li that
the SION bits will have to be enabled.

Hope this helps. Regards,
Nikolay