From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefano Babic Date: Sun, 15 Feb 2015 17:23:39 +0100 Subject: [U-Boot] [PATCH 1/4] mx6sx: pins: Enable SION for I2C3 iomux setting In-Reply-To: <54E0B71B.1080505@mail.bg> References: <1421052378-29913-1-git-send-email-B37916@freescale.com> <54B3A3D8.7010208@mail.bg> <54CA73C9.4000806@denx.de> <54D8B5DB.7040807@freescale.com> <54D9DB09.1020509@denx.de> <54E0B71B.1080505@mail.bg> Message-ID: <54E0C80B.5050309@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi everybody, On 15/02/2015 16:11, Nikolay Dimitrov wrote: >> Checked in manual, thanks for link. However, I have still a couple of >> questions. The controller can work as slave or as master, and according >> to the manual, the slave is the default after a reset. I understand that >> putting the controller into slave mode must require the SION bit set. >> Anyway, you are using I2C3 as master in your patch 4/4. Is it still >> mandatory even in this case to set the SION bit ? The manual states that >> to use the signal as input the SION bit must be set, but as far as I see >> in the patchset SCL is output only. > > Just tested the behavior of SION bit on imx6sl (riotboard), as I don't > have imx6sx hardware. > > For the test I used I2C4, located on expansion connector J13. I > verified that the SION bits are enabled after boot: > > # devregs IOMUXC_SW_MUX_CTL_PAD_GPIO07 > IOMUXC_SW_MUX_CTL_PAD_GPIO07:0x020e0238 =0x00000018 > > # devregs IOMUXC_SW_MUX_CTL_PAD_GPIO08 > IOMUXC_SW_MUX_CTL_PAD_GPIO08:0x020e023c =0x00000018 > > I also verified that the I2C interface works as expected (by observing > I2C transactions on a digital scope): > > i2cdetect -y 3 > > This works so far. Then I disabled the SION bits for both iomuxes: > > # devregs IOMUXC_SW_MUX_CTL_PAD_GPIO07 0x08 > IOMUXC_SW_MUX_CTL_PAD_GPIO07:0x020e0238 =0x00000018 > IOMUXC_SW_MUX_CTL_PAD_GPIO07:0x020e0238 == 0x00000018...0x00000008 > > # devregs IOMUXC_SW_MUX_CTL_PAD_GPIO08 0x08 > IOMUXC_SW_MUX_CTL_PAD_GPIO08:0x020e023c =0x00000018 > IOMUXC_SW_MUX_CTL_PAD_GPIO08:0x020e023c == 0x00000018...0x00000008 > > Now interface I2C4 doesn't work anymore. Instead of complete I2C > transactions, I see just a single pulses on both clock/data lines, > repeated on each 500ms. At the same time i2cdetect scans the address > space much more slowly than usual, and it looks like it timeouts on > each single address check for the same amount of time (500ms). > > Restoring the SION bits for clock & data restores the I2C4 > functionality. All the time the port was in master mode. > > I don't have experience with imx6sx, but if the I2C IP core was reused > for imx6sx (which is very likely), then I tend to agree with Ye Li that > the SION bits will have to be enabled. Thanks for testing and to share your experience. I will merge Li's patch now. Thanks again, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de =====================================================================