From mboxrd@z Thu Jan 1 00:00:00 1970 From: Troy Kisky Date: Mon, 16 Feb 2015 18:38:31 -0700 Subject: [U-Boot] [PATCH 2/4] mmc: fsl_esdhc: Add support to force VSELECT set In-Reply-To: <1424122683-29357-2-git-send-email-otavio@ossystems.com.br> References: <1424122683-29357-1-git-send-email-otavio@ossystems.com.br> <1424122683-29357-2-git-send-email-otavio@ossystems.com.br> Message-ID: <54E29B97.3000003@boundarydevices.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 2/16/2015 2:38 PM, Otavio Salvador wrote: > Some boards cannot do voltage negotiation but need to set the VSELECT > bit forcely to ensure it to work at 1.8V. > > This commit adds CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT flag for this use. > > Signed-off-by: Otavio Salvador > --- > > doc/README.fsl-esdhc | 1 + > drivers/mmc/fsl_esdhc.c | 4 ++++ > 2 files changed, 5 insertions(+) > > diff --git a/doc/README.fsl-esdhc b/doc/README.fsl-esdhc > index b70f271..619c6b2 100644 > --- a/doc/README.fsl-esdhc > +++ b/doc/README.fsl-esdhc > @@ -1,5 +1,6 @@ > CONFIG_SYS_FSL_ESDHC_LE means ESDHC IP is in little-endian mode. > CONFIG_SYS_FSL_ESDHC_BE means ESDHC IP is in big-endian mode. > +CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT forces to run at 1.8V. > > Accessing ESDHC registers can be determined by ESDHC IP's endian > mode or processor's endian mode. > diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c > index eb0fbf9..5fde2b6 100644 > --- a/drivers/mmc/fsl_esdhc.c > +++ b/drivers/mmc/fsl_esdhc.c > @@ -524,6 +524,10 @@ static int esdhc_init(struct mmc *mmc) > /* Set timout to the maximum value */ > esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); > > +#ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT > + esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); > +#endif > + > return 0; > } > > What if 1 controller needs it set and another needs it clear?