From mboxrd@z Thu Jan 1 00:00:00 1970 From: Hans de Goede Date: Thu, 19 Feb 2015 09:11:30 +0100 Subject: [U-Boot] [linux-sunxi] [UBOOT] Both Linux-Sunxi and Mainline Uboot have issues In-Reply-To: <3a04b33c-b203-4cff-bae8-6d0b5d2070d0@googlegroups.com> References: <3a04b33c-b203-4cff-bae8-6d0b5d2070d0@googlegroups.com> Message-ID: <54E59AB2.2060101@redhat.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi, On 19-02-15 07:29, TsvetanUsunov wrote: > Hi > > For A13-OLinuxino till now we conservatively used the Linux-Sunxi uboot, > but we recently got new lot of Samsung memories and we decided to tweak > some parameters for this DDR in Linux-Sunxi uboot and found problems. > As this uboot is with status not maintained anymore I will not discuss the > problems, as probably no one will spend time on it, so we wisely decided to > move to mainline uboot :) but it seems there are other issues to address. First of all let me say that it is a good decision to move to upstream u-boot, as one of the upstream u-boot Allwinner support maintainers I believe that that is a very good decision. In case you've not noticed yet upstream u-boot will give you a console on hdmi (or lcd if configured in the configs/A*-OLinuxIno*_defconfig file) and supports usb keyboards, so you can interact with u-boot without needing to hook up a serial console, and it supports booting from sata disks, and ... lets just say it is much better :) > The PLL5 and PLL6 values are changed and this cause problems, this is what > we found so far: > > > 1. mainline u-boot > ================= > 1.1 pll5 > address 0x01c20020, value 0xb1049091 - P=1, N=16, K=2, M=2. > The PLL5 output for DDR = (24MHz*N*K)/M. DDR=24*16*2/2 = 384MHz > The PLL5 output for other module = (24MHz*N*K)/P. DDR=24*16*2/1 = 768MHz - > This high frequency cause LCDs connected to the board to flicker pll5's clock was doubled in upstream u-boot to give downstream users more flexibility in which clocks they can get by dividing it. Unfortunately the allwinner derived linux-sunxi kernels have some hardcoded assumptions about pll5 speed left and right, so you must make sure that your kernel has these 2 commits: https://github.com/linux-sunxi/linux-sunxi/commit/9a1cd034181af628d4145202289e1993c1687db6 https://github.com/linux-sunxi/linux-sunxi/commit/ade08aa6e5249a9e75a97393e86c250b2bcb3ec8 Alternatively you can enable the old kernel compat option in u-boot's config, so you would do the following: make -j4 CROSS_COMPILE=arm-linux-gnu- A13-OLinuXino_defconfig make -j4 CROSS_COMPILE=arm-linux-gnu- menuconfig -> goto "ARM architecture" -> select "Enable workarounds for booting old kernels" -> exit -> exit -> save make -j4 CROSS_COMPILE=arm-linux-gnu- spl/menuconfig Do the same as for the normal menuconfig This will remove the doubling of the PLL5 speed. Note assuming you're using linux-sunxi kernels and not upstream kernels you also need "Enable workarounds for booting old kernels" for things to boot at all on A20 based devices, because the new u-boot by default boots the kernel in non secure mode (so that it can be a hypervisor and hw accelerated qemu-kvm works on the A20), but the old kernels do not work when booted in non secure mode (another bug in the old kernels, for which no fix is available). > 1.2 pll6 > address 0x01c20028, value 0xA1009900 - N=25, K=1, M=1 > The PLL6 output is (24MHz*N*K)/M/2 = 24*25*1/1/2 = 300MHz Actually with upstream u-boot the value is 0xA1009911, but the end result is the same: 24*25*2/2/2 = 300MHz > 1.3 MBUS clock > address 0x01c2015c, value 0x81000001 - MBUS clock source is PLL6/2 = 300/2 > = 150MHz - This is connected to PLL6 setup, at this 150 Mhz the board cant > play video smoothly and sometimes drop video packets when the video is > playing Hmm, interesting so it seems that PLL6 is different on the A13 compared to the A10/A20 and both upstream u-boot and the kernel get this wrong, and miss the extra /2 which is being done on the A13 only, causing this. I'll work on a fix for this and get back to you. Regards, Hans > 2. sunxi u-boot > ================= > 1.1 pll5 > address 0x01c20020, value 0xb1049091 - P=2, N=17, K=2, M=2. > The PLL5 output for DDR = (24MHz*N*K)/M. DDR=24*17*2/2 = 408MHz > The PLL5 output for other module = (24MHz*N*K)/P. DDR=24*16*2/2 = 408MHz - > this frequency was OK, There is no problem with LCD flickering, why the > frequency increase was necessary? > 1.2 pll6 > address 0x01c20028, value 0xA1009900 - N=25, K=1, M=1 > The PLL6 output is (24MHz*N*K)/M/2 = 24*25*1/1/2 = 300MHz > 1.3 about MBUS clock > address 0x01c2015c, value 0x82000001 - MBUS clock source is PLL5/2 = 408/2 > = 204MHz - at this frequency No packet drop when the video is playing > > > Can you tell me the reasons for the PLL5 and PLL6 frequency changes to > mainline uboot? > > Best regards > Tsvetan >