From mboxrd@z Thu Jan 1 00:00:00 1970 From: Hans de Goede Date: Fri, 20 Feb 2015 09:44:44 +0100 Subject: [U-Boot] [PATCH] sunxi: Fix sun5i mbus speed when booting old kernels In-Reply-To: <20150220101510.664a2c5c@i7> References: <1424354356-29523-1-git-send-email-hdegoede@redhat.com> <20150220101510.664a2c5c@i7> Message-ID: <54E6F3FC.80206@redhat.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi, On 20-02-15 09:15, Siarhei Siamashka wrote: > On Thu, 19 Feb 2015 14:59:16 +0100 > Hans de Goede wrote: > >> Older linux-sunxi-3.4 kernels override our PLL6 setting with 300 MHz, >> halving the mbus frequency, so set it to 300 MHz ourselves and base the >> mbus divider on that. >> >> Signed-off-by: Hans de Goede >> --- >> arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 9 +++++++++ >> 1 file changed, 9 insertions(+) >> >> diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h >> index d297ed0..c28ee05 100644 >> --- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h >> +++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h >> @@ -144,7 +144,16 @@ struct sunxi_ccm_reg { >> >> #define PLL1_CFG_DEFAULT 0xa1005000 >> >> +#if defined CONFIG_OLD_SUNXI_KERNEL_COMPAT && defined CONFIG_MACH_SUN5I >> +/* >> + * Older linux-sunxi-3.4 kernels override our PLL6 setting with 300 MHz, >> + * halving the mbus frequency, so set it to 300 MHz ourselves and base the >> + * mbus divider on that. >> + */ >> +#define PLL6_CFG_DEFAULT 0xa1009900 >> +#else >> #define PLL6_CFG_DEFAULT 0xa1009911 >> +#endif >> >> /* nand clock */ >> #define NAND_CLK_SRC_OSC24 0 > > Are there any good reasons to use 600MHz instead of 300MHz for PLL6 in > the default u-boot build? > > Maybe PLL6 can be just set to 300MHz for sun5i in all cases, regardless > of the CONFIG_OLD_SUNXI_KERNEL_COMPAT define? Basically the reasons are the same as why you want to keep PLL5 running at a high speed, PLL6 is a potential parent PLL for all mod0 clk using peripherals, and having it higher gives us more possible clocks. I agree that this (and the PLL5 speed) are an issue we need a better fix for then CONFIG_OLD_SUNXI_KERNEL_COMPAT if at all possible. I'll discuss this further as a reply to your: "[PATCH] sunxi: Machine id hack to prevent loading buggy sunxi-3.4 kernels" mail. Regards, Hans