* [U-Boot] [PATCH 0/3] board/seco: Add mx6q-uq7 basic board support
@ 2015-02-16 13:27 Boris Brezillon
2015-02-16 13:27 ` [U-Boot] [PATCH 1/3] ARM: mx6: move to a standard arch/board approach Boris Brezillon
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Boris Brezillon @ 2015-02-16 13:27 UTC (permalink / raw)
To: u-boot
Hello,
This series adds a preliminary support for SECO's iMX6 based boards.
The first 2 patches rework the way MX6 support is activated:
- avoid defining SoC variant and imximage.cfg file path in the
deprecated SYS_EXTRA_OPTIONS Kconfig option
- remove the need for the CONFIG_MX6 definition in each board
config header
Let me know if there already is some WIP to address those issues.
The last patch adds basic support for the mx6q/uq7 SECO board, and a
sane Kconfig skeleton for other SoC (Q, DL and S) and board (uQ7, Q7
and uSBC) variants.
Best Regards,
Boris
Boris Brezillon (3):
ARM: mx6: move to a standard arch/board approach
ARM: iMX: define an IMX_CONFIG Kconfig option
board/seco: Add mx6q-uq7 basic board support
arch/arm/Kconfig | 8 ++
arch/arm/cpu/armv7/mx6/Kconfig | 42 +++++++++
arch/arm/imx-common/Kconfig | 2 +
board/seco/Kconfig | 63 ++++++++++++++
board/seco/common/Makefile | 2 +
board/seco/common/mx6.c | 137 ++++++++++++++++++++++++++++++
board/seco/common/mx6.h | 9 ++
board/seco/mx6quq7/Makefile | 7 ++
board/seco/mx6quq7/mx6quq7-2g.cfg | 173 ++++++++++++++++++++++++++++++++++++++
board/seco/mx6quq7/mx6quq7.c | 165 ++++++++++++++++++++++++++++++++++++
configs/secomx6quq7_defconfig | 7 ++
include/configs/secomx6quq7.h | 162 +++++++++++++++++++++++++++++++++++
12 files changed, 777 insertions(+)
create mode 100644 arch/arm/cpu/armv7/mx6/Kconfig
create mode 100644 arch/arm/imx-common/Kconfig
create mode 100644 board/seco/Kconfig
create mode 100644 board/seco/common/Makefile
create mode 100644 board/seco/common/mx6.c
create mode 100644 board/seco/common/mx6.h
create mode 100644 board/seco/mx6quq7/Makefile
create mode 100644 board/seco/mx6quq7/mx6quq7-2g.cfg
create mode 100644 board/seco/mx6quq7/mx6quq7.c
create mode 100644 configs/secomx6quq7_defconfig
create mode 100644 include/configs/secomx6quq7.h
--
1.9.1
^ permalink raw reply [flat|nested] 6+ messages in thread* [U-Boot] [PATCH 1/3] ARM: mx6: move to a standard arch/board approach 2015-02-16 13:27 [U-Boot] [PATCH 0/3] board/seco: Add mx6q-uq7 basic board support Boris Brezillon @ 2015-02-16 13:27 ` Boris Brezillon 2015-02-16 13:27 ` [U-Boot] [PATCH 2/3] ARM: iMX: define an IMX_CONFIG Kconfig option Boris Brezillon 2015-02-16 13:27 ` [U-Boot] [PATCH 3/3] board/seco: Add mx6q-uq7 basic board support Boris Brezillon 2 siblings, 0 replies; 6+ messages in thread From: Boris Brezillon @ 2015-02-16 13:27 UTC (permalink / raw) To: u-boot Freescale boards are currently all defined in arch/arm/Kconfig, which makes them hard to detect. Moreover the MX6 SoC variant (Q, D, DL, S, SL) selection is currently done via the SYS_EXTRA_OPTIONS option which marked as deprecated. Move to a more standard way to select sub-architecture and board by creating a Kconfig under arch/arm/cpu/armv7/mx6 and a new ARCH_MX6 option. Existing MX6 board definitions should be moved in this new Kconfig in choice menu, and new boards should be directly declared in this menu. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> --- arch/arm/Kconfig | 6 ++++++ arch/arm/cpu/armv7/mx6/Kconfig | 31 +++++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+) create mode 100644 arch/arm/cpu/armv7/mx6/Kconfig diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 1f1ccad..7984bef 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -563,6 +563,10 @@ config ARCH_KEYSTONE select CPU_V7 select SUPPORT_SPL +config ARCH_MX6 + bool "Freescale MX6" + select CPU_V7 + config TARGET_M53EVK bool "Support m53evk" select CPU_V7 @@ -847,6 +851,8 @@ source "arch/arm/cpu/armv7/keystone/Kconfig" source "arch/arm/cpu/arm926ejs/kirkwood/Kconfig" +source "arch/arm/cpu/armv7/mx6/Kconfig" + source "arch/arm/cpu/arm926ejs/nomadik/Kconfig" source "arch/arm/cpu/armv7/omap3/Kconfig" diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig new file mode 100644 index 0000000..a32fd87 --- /dev/null +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -0,0 +1,31 @@ +if ARCH_MX6 + +config MX6 + bool + default y + +config MX6D + bool + +config MX6DL + bool + +config MX6Q + bool + +config MX6QDL + bool + +config MX6S + bool + +config MX6SL + bool + +config MX6SX + bool + +config SYS_SOC + default "mx6" + +endif -- 1.9.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 2/3] ARM: iMX: define an IMX_CONFIG Kconfig option 2015-02-16 13:27 [U-Boot] [PATCH 0/3] board/seco: Add mx6q-uq7 basic board support Boris Brezillon 2015-02-16 13:27 ` [U-Boot] [PATCH 1/3] ARM: mx6: move to a standard arch/board approach Boris Brezillon @ 2015-02-16 13:27 ` Boris Brezillon 2015-02-16 13:27 ` [U-Boot] [PATCH 3/3] board/seco: Add mx6q-uq7 basic board support Boris Brezillon 2 siblings, 0 replies; 6+ messages in thread From: Boris Brezillon @ 2015-02-16 13:27 UTC (permalink / raw) To: u-boot IMX_CONFIG is currently passed via the SYS_EXTRA_OPTIONS which is marked as deprecated. Add a new Kconfig file under arch/arm/imx-common and define the IMX_CONFIG Kconfig in there. Each board is supposed to provide a default value pointing to the appropriate imximage.cfg file. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> --- arch/arm/Kconfig | 2 ++ arch/arm/imx-common/Kconfig | 2 ++ 2 files changed, 4 insertions(+) create mode 100644 arch/arm/imx-common/Kconfig diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7984bef..429a6cc 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -877,6 +877,8 @@ source "arch/arm/cpu/armv7/zynq/Kconfig" source "arch/arm/cpu/armv7/Kconfig" +source "arch/arm/imx-common/Kconfig" + source "board/aristainetos/Kconfig" source "board/BuR/kwb/Kconfig" source "board/BuR/tseries/Kconfig" diff --git a/arch/arm/imx-common/Kconfig b/arch/arm/imx-common/Kconfig new file mode 100644 index 0000000..37b3752 --- /dev/null +++ b/arch/arm/imx-common/Kconfig @@ -0,0 +1,2 @@ +config IMX_CONFIG + string -- 1.9.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 3/3] board/seco: Add mx6q-uq7 basic board support 2015-02-16 13:27 [U-Boot] [PATCH 0/3] board/seco: Add mx6q-uq7 basic board support Boris Brezillon 2015-02-16 13:27 ` [U-Boot] [PATCH 1/3] ARM: mx6: move to a standard arch/board approach Boris Brezillon 2015-02-16 13:27 ` [U-Boot] [PATCH 2/3] ARM: iMX: define an IMX_CONFIG Kconfig option Boris Brezillon @ 2015-02-16 13:27 ` Boris Brezillon 2015-03-02 10:17 ` Stefano Babic 2 siblings, 1 reply; 6+ messages in thread From: Boris Brezillon @ 2015-02-16 13:27 UTC (permalink / raw) To: u-boot Add basic SECO MX6Q/uQ7 board support (Ethernet, UART, SD are supported). It also adds a Kconfig skeleton to later add more SECO board (supporting SoC and board variants). Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> --- arch/arm/cpu/armv7/mx6/Kconfig | 11 +++ board/seco/Kconfig | 63 ++++++++++++++ board/seco/common/Makefile | 2 + board/seco/common/mx6.c | 137 ++++++++++++++++++++++++++++++ board/seco/common/mx6.h | 9 ++ board/seco/mx6quq7/Makefile | 7 ++ board/seco/mx6quq7/mx6quq7-2g.cfg | 173 ++++++++++++++++++++++++++++++++++++++ board/seco/mx6quq7/mx6quq7.c | 165 ++++++++++++++++++++++++++++++++++++ configs/secomx6quq7_defconfig | 7 ++ include/configs/secomx6quq7.h | 162 +++++++++++++++++++++++++++++++++++ 10 files changed, 736 insertions(+) create mode 100644 board/seco/Kconfig create mode 100644 board/seco/common/Makefile create mode 100644 board/seco/common/mx6.c create mode 100644 board/seco/common/mx6.h create mode 100644 board/seco/mx6quq7/Makefile create mode 100644 board/seco/mx6quq7/mx6quq7-2g.cfg create mode 100644 board/seco/mx6quq7/mx6quq7.c create mode 100644 configs/secomx6quq7_defconfig create mode 100644 include/configs/secomx6quq7.h diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index a32fd87..076ba52 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -25,7 +25,18 @@ config MX6SL config MX6SX bool +choice + prompt "MX6 board select" + +config TARGET_SECOMX6 + bool "Support secomx6 boards" + select CPU_V7 + +endchoice + config SYS_SOC default "mx6" +source "board/seco/Kconfig" + endif diff --git a/board/seco/Kconfig b/board/seco/Kconfig new file mode 100644 index 0000000..dcb1ac8 --- /dev/null +++ b/board/seco/Kconfig @@ -0,0 +1,63 @@ +if TARGET_SECOMX6 + +choice + prompt "SECO i.MX6 Board variant" + +config SECOMX6_Q7 + bool "Q7" + +config SECOMX6_UQ7 + bool "uQ7" + +config SECOMX6_USBC + bool "uSBC" + +endchoice + +choice + prompt "SECO i.MX6 SoC variant" + +config SECOMX6Q + bool "i.MX6Q" + select MX6Q + +config SECOMX6DL + bool "i.MX6DL" + select MX6DL + +config SECOMX6S + bool "i.MX6S" + select MX6S + +endchoice + +choice + prompt "DDR size" + +config SECOMX6_512MB + bool "512MB" + +config SECOMX6_1GB + bool "1GB" + +config SECOMX6_2GB + bool "2GB" + +config SECOMX6_4GB + bool "4GB" + +endchoice + +config IMX_CONFIG + default "board/seco/mx6quq7/mx6quq7-2g.cfg" if SECOMX6_UQ7 && SECOMX6Q && SECOMX6_2GB + +config SYS_BOARD + default "mx6quq7" if SECOMX6_UQ7 && SECOMX6Q + +config SYS_VENDOR + default "seco" + +config SYS_CONFIG_NAME + default "secomx6quq7" if SECOMX6_UQ7 && SECOMX6Q + +endif diff --git a/board/seco/common/Makefile b/board/seco/common/Makefile new file mode 100644 index 0000000..9e37ebb --- /dev/null +++ b/board/seco/common/Makefile @@ -0,0 +1,2 @@ + +obj-$(CONFIG_TARGET_SECOMX6) += mx6.o diff --git a/board/seco/common/mx6.c b/board/seco/common/mx6.c new file mode 100644 index 0000000..40b8f56 --- /dev/null +++ b/board/seco/common/mx6.c @@ -0,0 +1,137 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * Copyright (C) 2015 ECA Sinters + * + * Author: Fabio Estevam <fabio.estevam@freescale.com> + * Modified by: Boris Brezillon <boris.brezillon@free-electrons.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/errno.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/boot_mode.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/arch/mxc_hdmi.h> +#include <asm/arch/crm_regs.h> +#include <linux/fb.h> +#include <ipu_pixfmt.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <micrel.h> +#include <asm/imx-common/mxc_i2c.h> +#include <i2c.h> + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +static iomux_v3_cfg_t const uart2_pads[] = { + MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +void seco_mx6_setup_uart_iomux(void) +{ + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); +} + +#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | \ + PAD_CTL_HYS) + +static iomux_v3_cfg_t const enet_pads[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +void seco_mx6_setup_enet_iomux(void) +{ + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); +} + +int seco_mx6_rgmii_rework(struct phy_device *phydev) +{ + /* control data pad skew - devaddr = 0x02, register = 0x04 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); + /* rx data pad skew - devaddr = 0x02, register = 0x05 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); + /* tx data pad skew - devaddr = 0x02, register = 0x05 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); + + /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF); + return 0; +} + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS) + +static iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc4_pads[] = { + MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +void seco_mx6_setup_usdhc_iomux(int id) +{ + switch (id) { + case 3: + imx_iomux_v3_setup_multiple_pads(usdhc3_pads, + ARRAY_SIZE(usdhc3_pads)); + break; + + case 4: + imx_iomux_v3_setup_multiple_pads(usdhc4_pads, + ARRAY_SIZE(usdhc4_pads)); + break; + + default: + break; + } +} diff --git a/board/seco/common/mx6.h b/board/seco/common/mx6.h new file mode 100644 index 0000000..a05db67 --- /dev/null +++ b/board/seco/common/mx6.h @@ -0,0 +1,9 @@ +#ifndef __SECO_COMMON_MX6_H +#define __SECO_COMMON_MX6_H + +void seco_mx6_setup_uart_iomux(void); +void seco_mx6_setup_enet_iomux(void); +int seco_mx6_rgmii_rework(struct phy_device *phydev); +void seco_mx6_setup_usdhc_iomux(int id); + +#endif /* __SECO_COMMON_MX6_H */ diff --git a/board/seco/mx6quq7/Makefile b/board/seco/mx6quq7/Makefile new file mode 100644 index 0000000..19f8d3a --- /dev/null +++ b/board/seco/mx6quq7/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2015 ECA Sinters +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx6q-uq7.o diff --git a/board/seco/mx6quq7/mx6quq7-2g.cfg b/board/seco/mx6quq7/mx6quq7-2g.cfg new file mode 100644 index 0000000..159120e --- /dev/null +++ b/board/seco/mx6quq7/mx6quq7-2g.cfg @@ -0,0 +1,173 @@ +/* + * Copyright (C) 2013 Seco USA Inc + * + * SPDX-License-Identifier: GPL-2.0 + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#define __ASSEMBLY__ +#include <config.h> +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +/* DDR IO TYPE */ +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 + +/* DATA STROBE */ +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000028 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000028 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000028 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000028 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000028 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000028 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000028 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000028 + +/* DATA */ +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 +DATA 4, MX6_IOM_GRP_B0DS, 0x00000028 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000028 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000028 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000028 +DATA 4, MX6_IOM_GRP_B4DS, 0x00000028 +DATA 4, MX6_IOM_GRP_B5DS, 0x00000028 +DATA 4, MX6_IOM_GRP_B6DS, 0x00000028 +DATA 4, MX6_IOM_GRP_B7DS, 0x00000028 +DATA 4, MX6_IOM_DRAM_DQM0, 0x00000028 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00000028 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00000028 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00000028 +DATA 4, MX6_IOM_DRAM_DQM4, 0x00000028 +DATA 4, MX6_IOM_DRAM_DQM5, 0x00000028 +DATA 4, MX6_IOM_DRAM_DQM6, 0x00000028 +DATA 4, MX6_IOM_DRAM_DQM7, 0x00000028 +/* ADDRESS */ +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000028 +DATA 4, MX6_IOM_DRAM_CAS, 0x00000028 +DATA 4, MX6_IOM_DRAM_RAS, 0x00000028 + +/* CONTROL */ +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 +DATA 4, MX6_IOM_DRAM_RESET, 0x00000028 +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000028 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000028 + +/* CLOCK */ +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000028 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000028 + +/* + * DDR3 SETTINGS + * Read Data Bit Delay + */ +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 + + +/* Write Leveling */ +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F0001 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F + +/* DQS gating, read delay, write delay calibration values */ +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x431A0326 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0323031B +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x433F0340 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x0345031C + +/* Read calibration */ +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x40343137 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x40372F45 + +/* write calibration */ +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x32414741 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4731473C + +/* Complete calibration by forced measurement: */ +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 + +/* + * MMDC init: + * in DDR3, 64-bit mode, only MMDC0 is init + */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 +DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 + +DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E7955 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB + +DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023 + +/* CS0_END = 2304MB in step da 256Mb -> [(2304*8/256) - 1] */ +DATA 4, MX6_MMDC_P0_MDASP, 0x00000047 + +/* SDE_1=0; ROW=3; BL=1; DSIZ=2 -> 64 bit */ +DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000 + +/* Initialize DDR3 on CS_0 and CS_1 */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x02088032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 + +/* P0 01c */ +/* write 0x0940 to MR0 bank_0 (Burst Type=1 (Interlived)) */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030 + +/*ZQ - Calibrationi */ +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MDREF, 0x00007800 + +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 + +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 + +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 + +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00C03F3F +DATA 4, CCM_CCGR1, 0x0030FC03 +DATA 4, CCM_CCGR2, 0x0FFFC000 +DATA 4, CCM_CCGR3, 0x3FF00000 +DATA 4, CCM_CCGR4, 0x00FFF300 +DATA 4, CCM_CCGR5, 0x0F0000C3 +DATA 4, CCM_CCGR6, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, MX6_IOMUXC_GPR4, 0xF00000FF + +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F + diff --git a/board/seco/mx6quq7/mx6quq7.c b/board/seco/mx6quq7/mx6quq7.c new file mode 100644 index 0000000..17942a3 --- /dev/null +++ b/board/seco/mx6quq7/mx6quq7.c @@ -0,0 +1,165 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * Copyright (C) 2015 ECA Sinters + * + * Author: Fabio Estevam <fabio.estevam@freescale.com> + * Modified by: Boris Brezillon <boris.brezillon@free-electrons.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/errno.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/boot_mode.h> +#include <malloc.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/arch/mxc_hdmi.h> +#include <asm/arch/crm_regs.h> +#include <linux/fb.h> +#include <ipu_pixfmt.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <micrel.h> +#include <asm/imx-common/mxc_i2c.h> +#include <i2c.h> + +#include "../common/mx6.h" + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +int board_early_init_f(void) +{ + seco_mx6_setup_uart_iomux(); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + seco_mx6_rgmii_rework(phydev); + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + uint32_t base = IMX_FEC_BASE; + struct mii_dev *bus = NULL; + struct phy_device *phydev = NULL; + int ret = 0; + + seco_mx6_setup_enet_iomux(); + +#ifdef CONFIG_FEC_MXC + bus = fec_get_miibus(base, -1); + if (!bus) + return -ENOMEM; + + /* scan phy 4,5,6,7 */ + phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII); + if (!phydev) { + free(bus); + return -ENOMEM; + } + + printf("using phy@%d\n", phydev->addr); + ret = fec_probe(bis, -1, base, bus, phydev); + if (ret) { + free(phydev); + free(bus); + printf("FEC MXC: %s:failed\n", __func__); + } +#endif + + return ret; +} + +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC3_BASE_ADDR}, + {USDHC2_BASE_ADDR}, +}; + +int board_mmc_init(bd_t *bis) +{ + int status = 0; + u32 index = 0; + + /* + * Following map is done: + * (U-boot device node) (Physical Port) + * mmc0 eMMC on Board + * mmc1 Ext SD + */ + for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { + switch (index) { + case 0: + seco_mx6_setup_usdhc_iomux(3); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[0].max_bus_width = 4; + break; + case 1: + seco_mx6_setup_usdhc_iomux(4); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + usdhc_cfg[1].max_bus_width = 4; + break; + + default: + printf("Warning: %d exceed maximum number of SD ports %d\n", + index + 1, CONFIG_SYS_FSL_USDHC_NUM); + return status; + } + + status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + } + + return status; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + imx_iomux_v3_setup_pad(MX6_PAD_NANDF_D4__GPIO2_IO04 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + + gpio_direction_output(IMX_GPIO_NR(2, 4), 0); + + /* Set Low */ + gpio_set_value(IMX_GPIO_NR(2, 4), 0); + udelay(1000); + + /* Set High */ + gpio_set_value(IMX_GPIO_NR(2, 4), 1); + + return 0; +} + +int board_late_init(void) +{ + return 0; +} + +int checkboard(void) +{ + puts("Board: SECO uQ7\n"); + + return 0; +} diff --git a/configs/secomx6quq7_defconfig b/configs/secomx6quq7_defconfig new file mode 100644 index 0000000..dcd681d --- /dev/null +++ b/configs/secomx6quq7_defconfig @@ -0,0 +1,7 @@ +CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_MMC" +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_SECOMX6=y +CONFIG_SECOMX6_UQ7=y +CONFIG_SECOMX6Q=y +CONFIG_SECOMX6_2GB=y diff --git a/include/configs/secomx6quq7.h b/include/configs/secomx6quq7.h new file mode 100644 index 0000000..0a4959e --- /dev/null +++ b/include/configs/secomx6quq7.h @@ -0,0 +1,162 @@ +/* + * Copyright (C) 2013 Seco S.r.l + * + * Configuration settings for the Seco Boards. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "mx6_common.h" +#include <asm/arch/imx-regs.h> +#include <asm/imx-common/gpio.h> +#include <linux/sizes.h> + +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_BOARD_REVISION_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART2_BASE + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Command definition */ +#include <config_cmd_default.h> + +#undef CONFIG_CMD_IMLS + +#define CONFIG_CMD_BMODE +#define CONFIG_CMD_SETEXPR + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M) +#define CONFIG_LOADADDR 0x12000000 +#define CONFIG_SYS_TEXT_BASE 0x17800000 + +/* MMC Configuration */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +/* Ethernet Configuration */ +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 6 +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "ethprime=FEC0\0" \ + "netdev=eth0\0" \ + "ethprime=FEC0\0" \ + "uboot=u-boot.bin\0" \ + "kernel=uImage\0" \ + "nfsroot=/opt/eldk/arm\0" \ + "ip_local=10.0.0.5::10.0.0.1:255.255.255.0::eth0:off\0" \ + "ip_server=10.0.0.1\0" \ + "nfs_path=/targetfs \0" \ + "memory=mem=1024M\0" \ + "bootdev=mmc dev 0; ext2load mmc 0:1\0" \ + "root=root=/dev/mmcblk0p1\0" \ + "option=rootwait rw fixrtc rootflags=barrier=1\0" \ + "cpu_freq=arm_freq=996\0" \ + "setbootargs=setenv bootargs console=ttymxc1,115200 ${root} ${option} ${memory} ${cpu_freq}\0" \ + "setbootargs_nfs=setenv bootargs console=ttymxc1,115200 root=/dev/nfs nfsroot=${ip_server}:${nfs_path} nolock,wsize=4096,rsize=4096 ip=:::::eth0:dhcp ${memory} ${cpu_freq}\0" \ + "setbootdev=setenv boot_dev ${bootdev} 10800000 /boot/uImage\0" \ + "bootcmd=run setbootargs; run setbootdev; run boot_dev; bootm 0x10800000\0" \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" + + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "SECO MX6Q uQ7 U-Boot > " + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING + + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024) + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_SIZE (8 * 1024) + +#if defined(CONFIG_ENV_IS_IN_MMC) + #define CONFIG_ENV_OFFSET (6 * 128 * 1024) + #define CONFIG_SYS_MMC_ENV_DEV 0 + #define CONFIG_DYNAMIC_MMC_DEVNO +#endif + +#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ + +#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE +#endif + +#endif /* __CONFIG_H */ -- 1.9.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 3/3] board/seco: Add mx6q-uq7 basic board support 2015-02-16 13:27 ` [U-Boot] [PATCH 3/3] board/seco: Add mx6q-uq7 basic board support Boris Brezillon @ 2015-03-02 10:17 ` Stefano Babic 2015-03-02 10:43 ` Boris Brezillon 0 siblings, 1 reply; 6+ messages in thread From: Stefano Babic @ 2015-03-02 10:17 UTC (permalink / raw) To: u-boot Hi Boris, On 16/02/2015 14:27, Boris Brezillon wrote: > Add basic SECO MX6Q/uQ7 board support (Ethernet, UART, SD are supported). > It also adds a Kconfig skeleton to later add more SECO board (supporting > SoC and board variants). > > Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> > --- > arch/arm/cpu/armv7/mx6/Kconfig | 11 +++ > board/seco/Kconfig | 63 ++++++++++++++ > board/seco/common/Makefile | 2 + > board/seco/common/mx6.c | 137 ++++++++++++++++++++++++++++++ > board/seco/common/mx6.h | 9 ++ > board/seco/mx6quq7/Makefile | 7 ++ > board/seco/mx6quq7/mx6quq7-2g.cfg | 173 ++++++++++++++++++++++++++++++++++++++ > board/seco/mx6quq7/mx6quq7.c | 165 ++++++++++++++++++++++++++++++++++++ > configs/secomx6quq7_defconfig | 7 ++ > include/configs/secomx6quq7.h | 162 +++++++++++++++++++++++++++++++++++ MAINTAINERS file is missing. I have tried your patches, I think there is something not coherent with names and the board cannot be built clean with buildman. Board is recognized as secomx6quq7, but then there is a mismatch in the board object library. You set: obj-y := mx6q-uq7.o but the source is mx6quq7.c and building breaks with make[1]: *** No rule to make target `board/seco/mx6quq7/mx6q-uq7.o', needed by `board/seco/mx6quq7/built-in.o'. Stop. Please take a look at it. > 10 files changed, 736 insertions(+) > create mode 100644 board/seco/Kconfig > create mode 100644 board/seco/common/Makefile > create mode 100644 board/seco/common/mx6.c > create mode 100644 board/seco/common/mx6.h > create mode 100644 board/seco/mx6quq7/Makefile > create mode 100644 board/seco/mx6quq7/mx6quq7-2g.cfg > create mode 100644 board/seco/mx6quq7/mx6quq7.c > create mode 100644 configs/secomx6quq7_defconfig > create mode 100644 include/configs/secomx6quq7.h > > diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig > index a32fd87..076ba52 100644 > --- a/arch/arm/cpu/armv7/mx6/Kconfig > +++ b/arch/arm/cpu/armv7/mx6/Kconfig > @@ -25,7 +25,18 @@ config MX6SL > config MX6SX > bool > > +choice > + prompt "MX6 board select" > + > +config TARGET_SECOMX6 > + bool "Support secomx6 boards" > + select CPU_V7 > + > +endchoice > + > config SYS_SOC > default "mx6" > > +source "board/seco/Kconfig" > + > endif > diff --git a/board/seco/Kconfig b/board/seco/Kconfig > new file mode 100644 > index 0000000..dcb1ac8 > --- /dev/null > +++ b/board/seco/Kconfig > @@ -0,0 +1,63 @@ > +if TARGET_SECOMX6 > + > +choice > + prompt "SECO i.MX6 Board variant" > + > +config SECOMX6_Q7 > + bool "Q7" > + > +config SECOMX6_UQ7 > + bool "uQ7" > + > +config SECOMX6_USBC > + bool "uSBC" > + > +endchoice > + > +choice > + prompt "SECO i.MX6 SoC variant" > + > +config SECOMX6Q > + bool "i.MX6Q" > + select MX6Q > + > +config SECOMX6DL > + bool "i.MX6DL" > + select MX6DL > + > +config SECOMX6S > + bool "i.MX6S" > + select MX6S > + > +endchoice > + > +choice > + prompt "DDR size" > + > +config SECOMX6_512MB > + bool "512MB" > + > +config SECOMX6_1GB > + bool "1GB" > + > +config SECOMX6_2GB > + bool "2GB" > + > +config SECOMX6_4GB > + bool "4GB" > + > +endchoice > + > +config IMX_CONFIG > + default "board/seco/mx6quq7/mx6quq7-2g.cfg" if SECOMX6_UQ7 && SECOMX6Q && SECOMX6_2GB > + > +config SYS_BOARD > + default "mx6quq7" if SECOMX6_UQ7 && SECOMX6Q > + > +config SYS_VENDOR > + default "seco" > + > +config SYS_CONFIG_NAME > + default "secomx6quq7" if SECOMX6_UQ7 && SECOMX6Q > + > +endif > diff --git a/board/seco/common/Makefile b/board/seco/common/Makefile > new file mode 100644 > index 0000000..9e37ebb > --- /dev/null > +++ b/board/seco/common/Makefile > @@ -0,0 +1,2 @@ > + > +obj-$(CONFIG_TARGET_SECOMX6) += mx6.o > diff --git a/board/seco/common/mx6.c b/board/seco/common/mx6.c > new file mode 100644 > index 0000000..40b8f56 > --- /dev/null > +++ b/board/seco/common/mx6.c > @@ -0,0 +1,137 @@ > +/* > + * Copyright (C) 2013 Freescale Semiconductor, Inc. > + * Copyright (C) 2015 ECA Sinters > + * > + * Author: Fabio Estevam <fabio.estevam@freescale.com> > + * Modified by: Boris Brezillon <boris.brezillon@free-electrons.com> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <asm/arch/clock.h> > +#include <asm/arch/imx-regs.h> > +#include <asm/arch/iomux.h> > +#include <asm/arch/mx6-pins.h> > +#include <asm/errno.h> > +#include <asm/gpio.h> > +#include <asm/imx-common/iomux-v3.h> > +#include <asm/imx-common/boot_mode.h> > +#include <mmc.h> > +#include <fsl_esdhc.h> > +#include <miiphy.h> > +#include <netdev.h> > +#include <asm/arch/mxc_hdmi.h> > +#include <asm/arch/crm_regs.h> > +#include <linux/fb.h> > +#include <ipu_pixfmt.h> > +#include <asm/io.h> > +#include <asm/arch/sys_proto.h> > +#include <micrel.h> > +#include <asm/imx-common/mxc_i2c.h> > +#include <i2c.h> > + > +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ > + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ > + PAD_CTL_SRE_FAST | PAD_CTL_HYS) > + > +static iomux_v3_cfg_t const uart2_pads[] = { > + MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), > + MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), > +}; > + > +void seco_mx6_setup_uart_iomux(void) > +{ > + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); > +} > + > +#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ > + PAD_CTL_SPEED_MED | \ > + PAD_CTL_DSE_40ohm | \ > + PAD_CTL_HYS) > + > +static iomux_v3_cfg_t const enet_pads[] = { > + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), > +}; > + > +void seco_mx6_setup_enet_iomux(void) > +{ > + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); > +} > + > +int seco_mx6_rgmii_rework(struct phy_device *phydev) > +{ > + /* control data pad skew - devaddr = 0x02, register = 0x04 */ > + ksz9031_phy_extended_write(phydev, 0x02, > + MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, > + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); > + /* rx data pad skew - devaddr = 0x02, register = 0x05 */ > + ksz9031_phy_extended_write(phydev, 0x02, > + MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, > + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); > + /* tx data pad skew - devaddr = 0x02, register = 0x05 */ > + ksz9031_phy_extended_write(phydev, 0x02, > + MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, > + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); > + > + /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */ > + ksz9031_phy_extended_write(phydev, 0x02, > + MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, > + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF); > + return 0; > +} > + > +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ > + PAD_CTL_SPEED_LOW | \ > + PAD_CTL_DSE_80ohm | \ > + PAD_CTL_SRE_FAST | \ > + PAD_CTL_HYS) > + > +static iomux_v3_cfg_t const usdhc3_pads[] = { > + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > +}; > + > +static iomux_v3_cfg_t const usdhc4_pads[] = { > + MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > +}; > + > +void seco_mx6_setup_usdhc_iomux(int id) > +{ > + switch (id) { > + case 3: > + imx_iomux_v3_setup_multiple_pads(usdhc3_pads, > + ARRAY_SIZE(usdhc3_pads)); > + break; > + > + case 4: > + imx_iomux_v3_setup_multiple_pads(usdhc4_pads, > + ARRAY_SIZE(usdhc4_pads)); > + break; > + > + default: Maybe it is better to print an error due to wrong id. > + break; > + } > +} > diff --git a/board/seco/common/mx6.h b/board/seco/common/mx6.h > new file mode 100644 > index 0000000..a05db67 > --- /dev/null > +++ b/board/seco/common/mx6.h > @@ -0,0 +1,9 @@ > +#ifndef __SECO_COMMON_MX6_H > +#define __SECO_COMMON_MX6_H > + > +void seco_mx6_setup_uart_iomux(void); > +void seco_mx6_setup_enet_iomux(void); > +int seco_mx6_rgmii_rework(struct phy_device *phydev); > +void seco_mx6_setup_usdhc_iomux(int id); > + > +#endif /* __SECO_COMMON_MX6_H */ > diff --git a/board/seco/mx6quq7/Makefile b/board/seco/mx6quq7/Makefile > new file mode 100644 > index 0000000..19f8d3a > --- /dev/null > +++ b/board/seco/mx6quq7/Makefile > @@ -0,0 +1,7 @@ > +# > +# (C) Copyright 2015 ECA Sinters > +# > +# SPDX-License-Identifier: GPL-2.0+ > +# > + > +obj-y := mx6q-uq7.o > diff --git a/board/seco/mx6quq7/mx6quq7-2g.cfg b/board/seco/mx6quq7/mx6quq7-2g.cfg > new file mode 100644 > index 0000000..159120e > --- /dev/null > +++ b/board/seco/mx6quq7/mx6quq7-2g.cfg > @@ -0,0 +1,173 @@ > +/* > + * Copyright (C) 2013 Seco USA Inc > + * > + * SPDX-License-Identifier: GPL-2.0 > + * > + * Refer doc/README.imximage for more details about how-to configure > + * and create imximage boot image > + * > + * The syntax is taken as close as possible with the kwbimage > + */ > + > +/* image version */ > +IMAGE_VERSION 2 > + > +/* > + * Boot Device : one of > + * spi, sd (the board has no nand neither onenand) > + */ > +BOOT_FROM sd > + > +#define __ASSEMBLY__ > +#include <config.h> > +#include "asm/arch/mx6-ddr.h" > +#include "asm/arch/iomux.h" > +#include "asm/arch/crm_regs.h" > + > +/* DDR IO TYPE */ > +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 > +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 > + > +/* DATA STROBE */ > +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 > +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000028 > +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000028 > +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000028 > +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000028 > +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000028 > +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000028 > +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000028 > +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000028 > + > +/* DATA */ > +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 > +DATA 4, MX6_IOM_GRP_B0DS, 0x00000028 > +DATA 4, MX6_IOM_GRP_B1DS, 0x00000028 > +DATA 4, MX6_IOM_GRP_B2DS, 0x00000028 > +DATA 4, MX6_IOM_GRP_B3DS, 0x00000028 > +DATA 4, MX6_IOM_GRP_B4DS, 0x00000028 > +DATA 4, MX6_IOM_GRP_B5DS, 0x00000028 > +DATA 4, MX6_IOM_GRP_B6DS, 0x00000028 > +DATA 4, MX6_IOM_GRP_B7DS, 0x00000028 > +DATA 4, MX6_IOM_DRAM_DQM0, 0x00000028 > +DATA 4, MX6_IOM_DRAM_DQM1, 0x00000028 > +DATA 4, MX6_IOM_DRAM_DQM2, 0x00000028 > +DATA 4, MX6_IOM_DRAM_DQM3, 0x00000028 > +DATA 4, MX6_IOM_DRAM_DQM4, 0x00000028 > +DATA 4, MX6_IOM_DRAM_DQM5, 0x00000028 > +DATA 4, MX6_IOM_DRAM_DQM6, 0x00000028 > +DATA 4, MX6_IOM_DRAM_DQM7, 0x00000028 > +/* ADDRESS */ > +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000028 > +DATA 4, MX6_IOM_DRAM_CAS, 0x00000028 > +DATA 4, MX6_IOM_DRAM_RAS, 0x00000028 > + > +/* CONTROL */ > +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 > +DATA 4, MX6_IOM_DRAM_RESET, 0x00000028 > +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 > +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000028 > +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000028 > + > +/* CLOCK */ > +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000028 > +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000028 > + > +/* > + * DDR3 SETTINGS > + * Read Data Bit Delay > + */ > +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 > +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 > +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 > +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 > +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 > +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 > +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 > +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 > + > + > +/* Write Leveling */ > +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F > +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F > +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F0001 > +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F > + > +/* DQS gating, read delay, write delay calibration values */ > +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x431A0326 > +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0323031B > +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x433F0340 > +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x0345031C > + > +/* Read calibration */ > +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x40343137 > +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x40372F45 > + > +/* write calibration */ > +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x32414741 > +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4731473C > + > +/* Complete calibration by forced measurement: */ > +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 > +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 > + > +/* > + * MMDC init: > + * in DDR3, 64-bit mode, only MMDC0 is init > + */ > +DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 > +DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 > + > +DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E7955 > +DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64 > +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB > + > +DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 > +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 > +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 > +DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023 > + > +/* CS0_END = 2304MB in step da 256Mb -> [(2304*8/256) - 1] */ > +DATA 4, MX6_MMDC_P0_MDASP, 0x00000047 > + > +/* SDE_1=0; ROW=3; BL=1; DSIZ=2 -> 64 bit */ > +DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000 > + > +/* Initialize DDR3 on CS_0 and CS_1 */ > +DATA 4, MX6_MMDC_P0_MDSCR, 0x02088032 > +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 > +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 > + > +/* P0 01c */ > +/* write 0x0940 to MR0 bank_0 (Burst Type=1 (Interlived)) */ > +DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030 > + > +/*ZQ - Calibrationi */ > +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003 > +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 > +DATA 4, MX6_MMDC_P0_MDREF, 0x00007800 > + > +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 > +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 > + > +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 > + > +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 > +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 > + > +/* set the default clock gate to save power */ > +DATA 4, CCM_CCGR0, 0x00C03F3F > +DATA 4, CCM_CCGR1, 0x0030FC03 > +DATA 4, CCM_CCGR2, 0x0FFFC000 > +DATA 4, CCM_CCGR3, 0x3FF00000 > +DATA 4, CCM_CCGR4, 0x00FFF300 > +DATA 4, CCM_CCGR5, 0x0F0000C3 > +DATA 4, CCM_CCGR6, 0x000003FF > + > +/* enable AXI cache for VDOA/VPU/IPU */ > +DATA 4, MX6_IOMUXC_GPR4, 0xF00000FF > + > +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ > +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F > +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F > + > diff --git a/board/seco/mx6quq7/mx6quq7.c b/board/seco/mx6quq7/mx6quq7.c > new file mode 100644 > index 0000000..17942a3 > --- /dev/null > +++ b/board/seco/mx6quq7/mx6quq7.c > @@ -0,0 +1,165 @@ > +/* > + * Copyright (C) 2013 Freescale Semiconductor, Inc. > + * Copyright (C) 2015 ECA Sinters > + * > + * Author: Fabio Estevam <fabio.estevam@freescale.com> > + * Modified by: Boris Brezillon <boris.brezillon@free-electrons.com> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <asm/arch/clock.h> > +#include <asm/arch/imx-regs.h> > +#include <asm/arch/iomux.h> > +#include <asm/arch/mx6-pins.h> > +#include <asm/errno.h> > +#include <asm/gpio.h> > +#include <asm/imx-common/iomux-v3.h> > +#include <asm/imx-common/boot_mode.h> > +#include <malloc.h> > +#include <mmc.h> > +#include <fsl_esdhc.h> > +#include <miiphy.h> > +#include <netdev.h> > +#include <asm/arch/mxc_hdmi.h> > +#include <asm/arch/crm_regs.h> > +#include <linux/fb.h> > +#include <ipu_pixfmt.h> > +#include <asm/io.h> > +#include <asm/arch/sys_proto.h> > +#include <micrel.h> > +#include <asm/imx-common/mxc_i2c.h> > +#include <i2c.h> > + > +#include "../common/mx6.h" > + > +DECLARE_GLOBAL_DATA_PTR; > + > +int dram_init(void) > +{ > + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); > + > + return 0; > +} > + > +int board_early_init_f(void) > +{ > + seco_mx6_setup_uart_iomux(); > + > + return 0; > +} > + > +int board_phy_config(struct phy_device *phydev) > +{ > + seco_mx6_rgmii_rework(phydev); > + if (phydev->drv->config) > + phydev->drv->config(phydev); > + > + return 0; > +} > + > +int board_eth_init(bd_t *bis) > +{ > + uint32_t base = IMX_FEC_BASE; > + struct mii_dev *bus = NULL; > + struct phy_device *phydev = NULL; > + int ret = 0; > + > + seco_mx6_setup_enet_iomux(); > + > +#ifdef CONFIG_FEC_MXC > + bus = fec_get_miibus(base, -1); > + if (!bus) > + return -ENOMEM; > + > + /* scan phy 4,5,6,7 */ > + phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII); > + if (!phydev) { > + free(bus); > + return -ENOMEM; > + } > + > + printf("using phy at %d\n", phydev->addr); > + ret = fec_probe(bis, -1, base, bus, phydev); > + if (ret) { > + free(phydev); > + free(bus); > + printf("FEC MXC: %s:failed\n", __func__); > + } > +#endif > + > + return ret; > +} > + > +static struct fsl_esdhc_cfg usdhc_cfg[2] = { > + {USDHC3_BASE_ADDR}, > + {USDHC2_BASE_ADDR}, > +}; > + > +int board_mmc_init(bd_t *bis) > +{ > + int status = 0; > + u32 index = 0; > + > + /* > + * Following map is done: > + * (U-boot device node) (Physical Port) > + * mmc0 eMMC on Board > + * mmc1 Ext SD > + */ > + for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { > + switch (index) { > + case 0: > + seco_mx6_setup_usdhc_iomux(3); > + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); > + usdhc_cfg[0].max_bus_width = 4; > + break; > + case 1: > + seco_mx6_setup_usdhc_iomux(4); > + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); > + usdhc_cfg[1].max_bus_width = 4; > + break; > + > + default: > + printf("Warning: %d exceed maximum number of SD ports %d\n", > + index + 1, CONFIG_SYS_FSL_USDHC_NUM); > + return status; > + } > + > + status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); Fabio cleaned up all for all boards these statement, check for example the sabresd. Instead of cumulating the error, the loop stops at the first failure. Do the same to be coherent. > + } > + > + return status; > +} > + > +int board_init(void) > +{ > + /* address of boot parameters */ > + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; > + > + imx_iomux_v3_setup_pad(MX6_PAD_NANDF_D4__GPIO2_IO04 | > + MUX_PAD_CTRL(NO_PAD_CTRL)); > + > + gpio_direction_output(IMX_GPIO_NR(2, 4), 0); > + Is it reset for phy ? Can you add a comment to explain what it is ? > + /* Set Low */ > + gpio_set_value(IMX_GPIO_NR(2, 4), 0); > + udelay(1000); > + > + /* Set High */ > + gpio_set_value(IMX_GPIO_NR(2, 4), 1); > + > + return 0; > +} > + > +int board_late_init(void) > +{ > + return 0; > +} Drop it, as well as CONFIG_BOARD_LATE_INIT > + > +int checkboard(void) > +{ > + puts("Board: SECO uQ7\n"); > + > + return 0; > +} > diff --git a/configs/secomx6quq7_defconfig b/configs/secomx6quq7_defconfig > new file mode 100644 > index 0000000..dcd681d > --- /dev/null > +++ b/configs/secomx6quq7_defconfig > @@ -0,0 +1,7 @@ > +CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_MMC" > +CONFIG_ARM=y > +CONFIG_ARCH_MX6=y > +CONFIG_TARGET_SECOMX6=y > +CONFIG_SECOMX6_UQ7=y > +CONFIG_SECOMX6Q=y > +CONFIG_SECOMX6_2GB=y > diff --git a/include/configs/secomx6quq7.h b/include/configs/secomx6quq7.h > new file mode 100644 > index 0000000..0a4959e > --- /dev/null > +++ b/include/configs/secomx6quq7.h > @@ -0,0 +1,162 @@ > +/* > + * Copyright (C) 2013 Seco S.r.l > + * > + * Configuration settings for the Seco Boards. > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#ifndef __CONFIG_H > +#define __CONFIG_H > + > +#include "mx6_common.h" > +#include <asm/arch/imx-regs.h> > +#include <asm/imx-common/gpio.h> > +#include <linux/sizes.h> > + > +#define CONFIG_SYS_GENERIC_BOARD > +#define CONFIG_DISPLAY_CPUINFO > +#define CONFIG_DISPLAY_BOARDINFO > + > +#define CONFIG_CMDLINE_TAG > +#define CONFIG_SETUP_MEMORY_TAGS > +#define CONFIG_INITRD_TAG > +#define CONFIG_REVISION_TAG > +#define CONFIG_BOARD_REVISION_TAG > + > +/* Size of malloc() pool */ > +#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) > + > +#define CONFIG_BOARD_EARLY_INIT_F > +#define CONFIG_BOARD_LATE_INIT > +#define CONFIG_MXC_GPIO > + > +#define CONFIG_MXC_UART > +#define CONFIG_MXC_UART_BASE UART2_BASE > + > +/* allow to overwrite serial and ethaddr */ > +#define CONFIG_ENV_OVERWRITE > +#define CONFIG_CONS_INDEX 1 > +#define CONFIG_BAUDRATE 115200 > + > +/* Command definition */ > +#include <config_cmd_default.h> > + > +#undef CONFIG_CMD_IMLS > + > +#define CONFIG_CMD_BMODE > +#define CONFIG_CMD_SETEXPR > + > +#define CONFIG_BOOTDELAY 3 > + > +#define CONFIG_SYS_MEMTEST_START 0x10000000 > +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M) > +#define CONFIG_LOADADDR 0x12000000 > +#define CONFIG_SYS_TEXT_BASE 0x17800000 > + > +/* MMC Configuration */ > +#define CONFIG_FSL_ESDHC > +#define CONFIG_FSL_USDHC > +#define CONFIG_SYS_FSL_USDHC_NUM 2 > +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 > + > +#define CONFIG_MMC > +#define CONFIG_CMD_MMC > +#define CONFIG_GENERIC_MMC > +#define CONFIG_BOUNCE_BUFFER > +#define CONFIG_CMD_EXT2 > +#define CONFIG_CMD_FAT > +#define CONFIG_DOS_PARTITION > + > +/* Ethernet Configuration */ > +#define CONFIG_CMD_PING > +#define CONFIG_CMD_DHCP > +#define CONFIG_CMD_MII > +#define CONFIG_CMD_NET > +#define CONFIG_FEC_MXC > +#define CONFIG_MII > +#define IMX_FEC_BASE ENET_BASE_ADDR > +#define CONFIG_FEC_XCV_TYPE RGMII > +#define CONFIG_ETHPRIME "FEC" > +#define CONFIG_FEC_MXC_PHYADDR 6 > +#define CONFIG_PHYLIB > +#define CONFIG_PHY_MICREL > + > +#define CONFIG_EXTRA_ENV_SETTINGS \ > + "netdev=eth0\0" \ > + "ethprime=FEC0\0" \ > + "netdev=eth0\0" \ > + "ethprime=FEC0\0" \ > + "uboot=u-boot.bin\0" \ > + "kernel=uImage\0" \ > + "nfsroot=/opt/eldk/arm\0" \ > + "ip_local=10.0.0.5::10.0.0.1:255.255.255.0::eth0:off\0" \ > + "ip_server=10.0.0.1\0" \ > + "nfs_path=/targetfs \0" \ > + "memory=mem=1024M\0" \ > + "bootdev=mmc dev 0; ext2load mmc 0:1\0" \ > + "root=root=/dev/mmcblk0p1\0" \ > + "option=rootwait rw fixrtc rootflags=barrier=1\0" \ > + "cpu_freq=arm_freq=996\0" \ > + "setbootargs=setenv bootargs console=ttymxc1,115200 ${root} ${option} ${memory} ${cpu_freq}\0" \ > + "setbootargs_nfs=setenv bootargs console=ttymxc1,115200 root=/dev/nfs nfsroot=${ip_server}:${nfs_path} nolock,wsize=4096,rsize=4096 ip=:::::eth0:dhcp ${memory} ${cpu_freq}\0" \ checkpatch is not very happy with these very long lines, can you fix them, please ? > + "setbootdev=setenv boot_dev ${bootdev} 10800000 /boot/uImage\0" \ > + "bootcmd=run setbootargs; run setbootdev; run boot_dev; bootm 0x10800000\0" \ > + "stdin=serial\0" \ > + "stdout=serial\0" \ > + "stderr=serial\0" > + > + > +/* Miscellaneous configurable options */ > +#define CONFIG_SYS_LONGHELP > +#define CONFIG_SYS_HUSH_PARSER > +#define CONFIG_SYS_PROMPT "SECO MX6Q uQ7 U-Boot > " > + > +#define CONFIG_AUTO_COMPLETE > +#define CONFIG_SYS_CBSIZE 256 > + > +/* Print Buffer Size */ > +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ > + sizeof(CONFIG_SYS_PROMPT) + 16) > +#define CONFIG_SYS_MAXARGS 16 > +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE > + > +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR > +#define CONFIG_SYS_HZ 1000 > + > +#define CONFIG_CMDLINE_EDITING > + > + > +/* Physical Memory Map */ > +#define CONFIG_NR_DRAM_BANKS 1 > +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR > +#define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024) > + > +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM > +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR > +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE > + > +#define CONFIG_SYS_INIT_SP_OFFSET \ > + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) > +#define CONFIG_SYS_INIT_SP_ADDR \ > + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) > + > +/* FLASH and environment organization */ > +#define CONFIG_SYS_NO_FLASH > + > +#define CONFIG_ENV_SIZE (8 * 1024) > + > +#if defined(CONFIG_ENV_IS_IN_MMC) > + #define CONFIG_ENV_OFFSET (6 * 128 * 1024) > + #define CONFIG_SYS_MMC_ENV_DEV 0 > + #define CONFIG_DYNAMIC_MMC_DEVNO > +#endif > + > +#define CONFIG_OF_LIBFDT > +#define CONFIG_CMD_BOOTZ > + > +#ifndef CONFIG_SYS_DCACHE_OFF > +#define CONFIG_CMD_CACHE > +#endif > + > +#endif /* __CONFIG_H */ > Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 3/3] board/seco: Add mx6q-uq7 basic board support 2015-03-02 10:17 ` Stefano Babic @ 2015-03-02 10:43 ` Boris Brezillon 0 siblings, 0 replies; 6+ messages in thread From: Boris Brezillon @ 2015-03-02 10:43 UTC (permalink / raw) To: u-boot Hi Stefano, On Mon, 02 Mar 2015 11:17:42 +0100 Stefano Babic <sbabic@denx.de> wrote: > Hi Boris, > > On 16/02/2015 14:27, Boris Brezillon wrote: > > Add basic SECO MX6Q/uQ7 board support (Ethernet, UART, SD are supported). > > It also adds a Kconfig skeleton to later add more SECO board (supporting > > SoC and board variants). > > > > Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> > > --- > > arch/arm/cpu/armv7/mx6/Kconfig | 11 +++ > > board/seco/Kconfig | 63 ++++++++++++++ > > board/seco/common/Makefile | 2 + > > board/seco/common/mx6.c | 137 ++++++++++++++++++++++++++++++ > > board/seco/common/mx6.h | 9 ++ > > board/seco/mx6quq7/Makefile | 7 ++ > > board/seco/mx6quq7/mx6quq7-2g.cfg | 173 ++++++++++++++++++++++++++++++++++++++ > > board/seco/mx6quq7/mx6quq7.c | 165 ++++++++++++++++++++++++++++++++++++ > > configs/secomx6quq7_defconfig | 7 ++ > > include/configs/secomx6quq7.h | 162 +++++++++++++++++++++++++++++++++++ > > MAINTAINERS file is missing. > > I have tried your patches, I think there is something not coherent with > names and the board cannot be built clean with buildman. Board is > recognized as secomx6quq7, but then there is a mismatch in the board > object library. > > You set: > > obj-y := mx6q-uq7.o > > > but the source is mx6quq7.c and building breaks with > > make[1]: *** No rule to make target `board/seco/mx6quq7/mx6q-uq7.o', > needed by `board/seco/mx6quq7/built-in.o'. Stop. Indeed. I renamed all the files to match what's done for other boards (no dashes or underscores in names), but apparently forgot to change it in the Makefile. I didn't notice it when compiling because I still add an mx6q-uq7.o file in my directory. Anyway, I'll fix that. [...] > > +void seco_mx6_setup_usdhc_iomux(int id) > > +{ > > + switch (id) { > > + case 3: > > + imx_iomux_v3_setup_multiple_pads(usdhc3_pads, > > + ARRAY_SIZE(usdhc3_pads)); > > + break; > > + > > + case 4: > > + imx_iomux_v3_setup_multiple_pads(usdhc4_pads, > > + ARRAY_SIZE(usdhc4_pads)); > > + break; > > + > > + default: > > Maybe it is better to print an error due to wrong id. Sure, I'll add an error message. [...] > > +int board_mmc_init(bd_t *bis) > > +{ > > + int status = 0; > > + u32 index = 0; > > + > > + /* > > + * Following map is done: > > + * (U-boot device node) (Physical Port) > > + * mmc0 eMMC on Board > > + * mmc1 Ext SD > > + */ > > + for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { > > + switch (index) { > > + case 0: > > + seco_mx6_setup_usdhc_iomux(3); > > + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); > > + usdhc_cfg[0].max_bus_width = 4; > > + break; > > + case 1: > > + seco_mx6_setup_usdhc_iomux(4); > > + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); > > + usdhc_cfg[1].max_bus_width = 4; > > + break; > > + > > + default: > > + printf("Warning: %d exceed maximum number of SD ports %d\n", > > + index + 1, CONFIG_SYS_FSL_USDHC_NUM); > > + return status; > > + } > > + > > + status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); > > Fabio cleaned up all for all boards these statement, check for example > the sabresd. Instead of cumulating the error, the loop stops at the > first failure. Do the same to be coherent. Okay, I'll have a look. > > > + } > > + > > + return status; > > +} > > + > > +int board_init(void) > > +{ > > + /* address of boot parameters */ > > + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; > > + > > + imx_iomux_v3_setup_pad(MX6_PAD_NANDF_D4__GPIO2_IO04 | > > + MUX_PAD_CTRL(NO_PAD_CTRL)); > > + > > + gpio_direction_output(IMX_GPIO_NR(2, 4), 0); > > + > > Is it reset for phy ? Can you add a comment to explain what it is ? I don't know what this pin is controlling, but if I don't do the following toggle sequence, the board hangs. Note that I don't have the schematics of this board, and all my work is based on SECO's BSP. > > > + /* Set Low */ > > + gpio_set_value(IMX_GPIO_NR(2, 4), 0); > > + udelay(1000); > > + > > + /* Set High */ > > + gpio_set_value(IMX_GPIO_NR(2, 4), 1); > > + > > + return 0; > > +} > > + > > +int board_late_init(void) > > +{ > > + return 0; > > +} > > Drop it, as well as CONFIG_BOARD_LATE_INIT Ok. [...] > > +#define CONFIG_EXTRA_ENV_SETTINGS \ > > + "netdev=eth0\0" \ > > + "ethprime=FEC0\0" \ > > + "netdev=eth0\0" \ > > + "ethprime=FEC0\0" \ > > + "uboot=u-boot.bin\0" \ > > + "kernel=uImage\0" \ > > + "nfsroot=/opt/eldk/arm\0" \ > > + "ip_local=10.0.0.5::10.0.0.1:255.255.255.0::eth0:off\0" \ > > + "ip_server=10.0.0.1\0" \ > > + "nfs_path=/targetfs \0" \ > > + "memory=mem=1024M\0" \ > > + "bootdev=mmc dev 0; ext2load mmc 0:1\0" \ > > + "root=root=/dev/mmcblk0p1\0" \ > > + "option=rootwait rw fixrtc rootflags=barrier=1\0" \ > > + "cpu_freq=arm_freq=996\0" \ > > + "setbootargs=setenv bootargs console=ttymxc1,115200 ${root} ${option} ${memory} ${cpu_freq}\0" \ > > + "setbootargs_nfs=setenv bootargs console=ttymxc1,115200 root=/dev/nfs nfsroot=${ip_server}:${nfs_path} nolock,wsize=4096,rsize=4096 ip=:::::eth0:dhcp ${memory} ${cpu_freq}\0" \ > > checkpatch is not very happy with these very long lines, can you fix > them, please ? Yes I know, I just wasn't sure if there was a rule like 'do not split bootargs definitions in multi-line strings'. I'll split the lines appropriately. > > > + "setbootdev=setenv boot_dev ${bootdev} 10800000 /boot/uImage\0" \ > > + "bootcmd=run setbootargs; run setbootdev; run boot_dev; bootm 0x10800000\0" \ > > + "stdin=serial\0" \ > > + "stdout=serial\0" \ > > + "stderr=serial\0" > > + > > + > > +/* Miscellaneous configurable options */ > > +#define CONFIG_SYS_LONGHELP > > +#define CONFIG_SYS_HUSH_PARSER > > +#define CONFIG_SYS_PROMPT "SECO MX6Q uQ7 U-Boot > " > > + > > +#define CONFIG_AUTO_COMPLETE > > +#define CONFIG_SYS_CBSIZE 256 > > + > > +/* Print Buffer Size */ > > +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ > > + sizeof(CONFIG_SYS_PROMPT) + 16) > > +#define CONFIG_SYS_MAXARGS 16 > > +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE > > + > > +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR > > +#define CONFIG_SYS_HZ 1000 > > + > > +#define CONFIG_CMDLINE_EDITING > > + > > + > > +/* Physical Memory Map */ > > +#define CONFIG_NR_DRAM_BANKS 1 > > +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR > > +#define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024) > > + > > +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM > > +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR > > +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE > > + > > +#define CONFIG_SYS_INIT_SP_OFFSET \ > > + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) > > +#define CONFIG_SYS_INIT_SP_ADDR \ > > + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) > > + > > +/* FLASH and environment organization */ > > +#define CONFIG_SYS_NO_FLASH > > + > > +#define CONFIG_ENV_SIZE (8 * 1024) > > + > > +#if defined(CONFIG_ENV_IS_IN_MMC) > > + #define CONFIG_ENV_OFFSET (6 * 128 * 1024) > > + #define CONFIG_SYS_MMC_ENV_DEV 0 > > + #define CONFIG_DYNAMIC_MMC_DEVNO > > +#endif > > + > > +#define CONFIG_OF_LIBFDT > > +#define CONFIG_CMD_BOOTZ > > + > > +#ifndef CONFIG_SYS_DCACHE_OFF > > +#define CONFIG_CMD_CACHE > > +#endif > > + > > +#endif /* __CONFIG_H */ > > > Thanks for your review. Best Regards, Boris -- Boris Brezillon, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2015-03-02 10:43 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2015-02-16 13:27 [U-Boot] [PATCH 0/3] board/seco: Add mx6q-uq7 basic board support Boris Brezillon 2015-02-16 13:27 ` [U-Boot] [PATCH 1/3] ARM: mx6: move to a standard arch/board approach Boris Brezillon 2015-02-16 13:27 ` [U-Boot] [PATCH 2/3] ARM: iMX: define an IMX_CONFIG Kconfig option Boris Brezillon 2015-02-16 13:27 ` [U-Boot] [PATCH 3/3] board/seco: Add mx6q-uq7 basic board support Boris Brezillon 2015-03-02 10:17 ` Stefano Babic 2015-03-02 10:43 ` Boris Brezillon
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