From mboxrd@z Thu Jan  1 00:00:00 1970
From: Stefan Roese <sr@denx.de>
Date: Thu, 05 Mar 2015 17:30:26 +0100
Subject: [U-Boot] [PATCH 2/2] spi: Add Cadence QSPI controller Kconfig
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In-Reply-To: <201503051714.31249.marex@denx.de>
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On 05.03.2015 17:14, Marek Vasut wrote:
>>> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
>>> index c0b2570..eaf31ed 100644
>>> --- a/drivers/spi/Kconfig
>>> +++ b/drivers/spi/Kconfig
>>> @@ -16,3 +16,9 @@ config DESIGNWARE_SPI
>>>
>>>          depends on DM_SPI
>>>          help
>>>
>>>            Enable the Designware SPI driver.
>>>
>>> +
>>> +config CADENCE_QSPI
>>> +       bool "Cadence QSPI driver"
>>> +       depends on DM_SPI
>>> +       help
>>> +         Enable the Cadence QSPI driver.
>>
>> Can we get a bit more detail here? What does QSPI mean? What features
>> does it support?
>
> Stefan ? ;-)

Its the IP core from Cadence supporting SPI NOR flash and is present on 
the Altera SoCFPGA. Enabling access to such SPI NOR flash devices. QSPI 
stands for Quad-SPI and refers to the optional use of up to 4 data lines 
for flash access.

So perhaps something like this:

+
+config CADENCE_QSPI
+	bool "Cadence QSPI driver"
+	depends on DM_SPI
+	help
+	  Enable the Cadence QSPI driver. This driver can be used to +	 
access the SPI NOR flash on platforms embedding this
+	  Cadence IP core (like the Altera SoCFPGA). QSPI stands for
+	  Quad-SPI and refers to the optional use of up to 4 data lines
+	  for flash access.

HTP.

Thanks,
Stefan