From mboxrd@z Thu Jan  1 00:00:00 1970
From: Nishanth Menon <nm@ti.com>
Date: Fri, 6 Mar 2015 11:33:12 -0600
Subject: [U-Boot] [PATCH V5 09/11] ARM: OMAP5 / DRA7: Setup L2 Aux
 Control Register with recommended configuration
In-Reply-To: <20150306170553.GB17895@bill-the-cat>
References: <1425616866-11702-1-git-send-email-nm@ti.com>
 <1425616866-11702-10-git-send-email-nm@ti.com>
 <20150306170553.GB17895@bill-the-cat>
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On 03/06/2015 11:05 AM, Tom Rini wrote:
> On Thu, Mar 05, 2015 at 10:41:04PM -0600, Nishanth Menon wrote:
> 
>> Update to existing recommendation for L2ACTLR configuration to prevent
>> system instability and optimize performance.
>>
>> These apply to both OMAP5 and DRA7.
>>
>> Reported-by: Vivek Chengalvala <vchengalvala@ti.com>
>> Signed-off-by: Nishanth Menon <nm@ti.com>
>> ---
>>  arch/arm/cpu/armv7/omap5/hwinit.c |   16 ++++++++++++++++
>>  1 file changed, 16 insertions(+)
>>
>> diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
>> index f8060555b680..8d6b59eeb044 100644
>> --- a/arch/arm/cpu/armv7/omap5/hwinit.c
>> +++ b/arch/arm/cpu/armv7/omap5/hwinit.c
>> @@ -304,6 +304,21 @@ void config_data_eye_leveling_samples(u32 emif_base)
>>  		       (*ctrl)->control_emif2_sdram_config_ext);
>>  }
>>  
>> +void init_cpu_configuration(void)
>> +{
>> +	u32 l2actlr;
>> +
>> +	asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r"(l2actlr));
>> +	/*
>> +	 * L2ACTLR: Ensure to enable the following:
>> +	 * 3: Disable clean/evict push to external
>> +	 * 4: Disable WriteUnique and WriteLineUnique transactions from master
>> +	 * 8: Disable DVM/CMO message broadcast
>> +	 */
>> +	l2actlr |= 0x118;
>> +	omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2actlr);
>> +}
>> +
> 
> The function should at least be marked as static.  I don't see a better
> place for this since we want these bits set sooner rather than later so
> board_late_init or whatever is probably not super awesome as there's
> probably some corner case where we'll get bit, right?
> 
yeah - i did consider late_init, then realized that folks might want
to turn on l2 cache, just like they did on cortex-a8 beagle, which'd
mean l2actlr modifications(if done in late_init) with cache on is not
really a good idea, instead stuck with init of omap revision - which
is as early as I could get for a logical place on SoC code.

-- 
Regards,
Nishanth Menon