From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Date: Tue, 2 Feb 2021 09:05:53 +0100 Subject: [PATCH] nvme: Fix cache alignment In-Reply-To: References: <20210130175340.114209-1-marek.vasut+renesas@gmail.com> Message-ID: <54df757b-9a87-e2bb-5d29-2b640075e7f5@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 2/2/21 4:55 AM, Bin Meng wrote: Hi, >> The various structures in the driver are already correcty padded and > > typo: correctly > >> cache aligned in memory, however the cache operations are called on >> the structure sizes, which themselves might not be cache aligned. Add >> the necessary rounding to fix this, which permits the nvme to work on >> arm64. > > +ARM guys > > Which ARM64 SoC did you test this with? RCar3, although that's irrelevant, the problem will happen on any arm or arm64, and possibly any other system which needs cache management. > The round down in this patch should be unnecessary. Can you explain why ? > But it's better to > figure out which call to dcache_xxx() with an unaligned end address. If you look at the code, most of them can (and do) trigger this, therefore they need such alignment, as explained in the commit message. [...]