* [U-Boot] [PATCH 1/4] ARM: atmel: arm926ejs: fix clock configuration
2015-03-13 9:19 [U-Boot] [PATCH 0/4] ARM: atmel: boards: enable SPL support Bo Shen
@ 2015-03-13 9:19 ` Bo Shen
2015-03-17 7:45 ` Heiko Schocher
2015-03-13 9:19 ` [U-Boot] [PATCH 2/4] ARM: atmel: at91sam9m10g45ek: enable spl support Bo Shen
` (2 subsequent siblings)
3 siblings, 1 reply; 10+ messages in thread
From: Bo Shen @ 2015-03-13 9:19 UTC (permalink / raw)
To: u-boot
Config MCKR according to the datasheet sequence, or else it
will cause the MCKR configuration failed.
Remove timeout checking for clock configuration, if configure
the clock failed, let the system hang while not run in wrong
clock configuration.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
---
arch/arm/mach-at91/arm926ejs/clock.c | 54 +++++++++++++++++++-----------------
1 file changed, 28 insertions(+), 26 deletions(-)
diff --git a/arch/arm/mach-at91/arm926ejs/clock.c b/arch/arm/mach-at91/arm926ejs/clock.c
index f363982..8d6934e 100644
--- a/arch/arm/mach-at91/arm926ejs/clock.c
+++ b/arch/arm/mach-at91/arm926ejs/clock.c
@@ -195,50 +195,52 @@ int at91_clock_init(unsigned long main_clock)
void at91_plla_init(u32 pllar)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
- int timeout = AT91_PLL_LOCK_TIMEOUT;
writel(pllar, &pmc->pllar);
- while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY))) {
- timeout--;
- if (timeout == 0)
- break;
- }
+ while (!(readl(&pmc->sr) & AT91_PMC_LOCKA))
+ ;
}
void at91_pllb_init(u32 pllbr)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
- int timeout = AT91_PLL_LOCK_TIMEOUT;
writel(pllbr, &pmc->pllbr);
- while (!(readl(&pmc->sr) & (AT91_PMC_LOCKB | AT91_PMC_MCKRDY))) {
- timeout--;
- if (timeout == 0)
- break;
- }
+ while (!(readl(&pmc->sr) & AT91_PMC_LOCKB))
+ ;
}
void at91_mck_init(u32 mckr)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
- int timeout = AT91_PLL_LOCK_TIMEOUT;
u32 tmp;
tmp = readl(&pmc->mckr);
- tmp &= ~(AT91_PMC_MCKR_PRES_MASK |
- AT91_PMC_MCKR_MDIV_MASK |
- AT91_PMC_MCKR_PLLADIV_MASK |
- AT91_PMC_MCKR_CSS_MASK);
- tmp |= mckr & (AT91_PMC_MCKR_PRES_MASK |
- AT91_PMC_MCKR_MDIV_MASK |
- AT91_PMC_MCKR_PLLADIV_MASK |
- AT91_PMC_MCKR_CSS_MASK);
+ tmp &= ~AT91_PMC_MCKR_PRES_MASK;
+ tmp |= mckr & AT91_PMC_MCKR_PRES_MASK;
writel(tmp, &pmc->mckr);
+ while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
+ ;
- while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) {
- timeout--;
- if (timeout == 0)
- break;
- }
+ tmp = readl(&pmc->mckr);
+ tmp &= ~AT91_PMC_MCKR_MDIV_MASK;
+ tmp |= mckr & AT91_PMC_MCKR_MDIV_MASK;
+ writel(tmp, &pmc->mckr);
+ while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
+ ;
+
+ tmp = readl(&pmc->mckr);
+ tmp &= ~AT91_PMC_MCKR_PLLADIV_MASK;
+ tmp |= mckr & AT91_PMC_MCKR_PLLADIV_MASK;
+ writel(tmp, &pmc->mckr);
+ while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
+ ;
+
+ tmp = readl(&pmc->mckr);
+ tmp &= ~AT91_PMC_MCKR_CSS_MASK;
+ tmp |= mckr & AT91_PMC_MCKR_CSS_MASK;
+ writel(tmp, &pmc->mckr);
+ while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
+ ;
}
void at91_periph_clk_enable(int id)
--
2.3.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* [U-Boot] [PATCH 1/4] ARM: atmel: arm926ejs: fix clock configuration
2015-03-13 9:19 ` [U-Boot] [PATCH 1/4] ARM: atmel: arm926ejs: fix clock configuration Bo Shen
@ 2015-03-17 7:45 ` Heiko Schocher
2015-03-17 7:58 ` Bo Shen
0 siblings, 1 reply; 10+ messages in thread
From: Heiko Schocher @ 2015-03-17 7:45 UTC (permalink / raw)
To: u-boot
Hello Bo,
Am 13.03.2015 10:19, schrieb Bo Shen:
> Config MCKR according to the datasheet sequence, or else it
> will cause the MCKR configuration failed.
>
> Remove timeout checking for clock configuration, if configure
> the clock failed, let the system hang while not run in wrong
> clock configuration.
>
> Signed-off-by: Bo Shen <voice.shen@atmel.com>
> ---
>
> arch/arm/mach-at91/arm926ejs/clock.c | 54 +++++++++++++++++++-----------------
> 1 file changed, 28 insertions(+), 26 deletions(-)
Tested on the corvus and taurus board.
Tested-by: Heiko Schocher <hs@denx.de>
> diff --git a/arch/arm/mach-at91/arm926ejs/clock.c b/arch/arm/mach-at91/arm926ejs/clock.c
> index f363982..8d6934e 100644
> --- a/arch/arm/mach-at91/arm926ejs/clock.c
> +++ b/arch/arm/mach-at91/arm926ejs/clock.c
> @@ -195,50 +195,52 @@ int at91_clock_init(unsigned long main_clock)
> void at91_plla_init(u32 pllar)
> {
> struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
> - int timeout = AT91_PLL_LOCK_TIMEOUT;
>
> writel(pllar, &pmc->pllar);
> - while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY))) {
> - timeout--;
> - if (timeout == 0)
> - break;
> - }
> + while (!(readl(&pmc->sr) & AT91_PMC_LOCKA))
> + ;
just hanging is maybe also bad ... could we hang with adding a
if (timeout == 0) {
debug("could not set PLL(A|B)\n");
timeout = AT91_PLL_LOCK_TIMEOUT;
}
Thinking about it ... have we setup here the debug uart already?
If not, forget my comment
bye,
Heiko
> }
> void at91_pllb_init(u32 pllbr)
> {
> struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
> - int timeout = AT91_PLL_LOCK_TIMEOUT;
>
> writel(pllbr, &pmc->pllbr);
> - while (!(readl(&pmc->sr) & (AT91_PMC_LOCKB | AT91_PMC_MCKRDY))) {
> - timeout--;
> - if (timeout == 0)
> - break;
> - }
> + while (!(readl(&pmc->sr) & AT91_PMC_LOCKB))
> + ;
> }
>
> void at91_mck_init(u32 mckr)
> {
> struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
> - int timeout = AT91_PLL_LOCK_TIMEOUT;
> u32 tmp;
>
> tmp = readl(&pmc->mckr);
> - tmp &= ~(AT91_PMC_MCKR_PRES_MASK |
> - AT91_PMC_MCKR_MDIV_MASK |
> - AT91_PMC_MCKR_PLLADIV_MASK |
> - AT91_PMC_MCKR_CSS_MASK);
> - tmp |= mckr & (AT91_PMC_MCKR_PRES_MASK |
> - AT91_PMC_MCKR_MDIV_MASK |
> - AT91_PMC_MCKR_PLLADIV_MASK |
> - AT91_PMC_MCKR_CSS_MASK);
> + tmp &= ~AT91_PMC_MCKR_PRES_MASK;
> + tmp |= mckr & AT91_PMC_MCKR_PRES_MASK;
> writel(tmp, &pmc->mckr);
> + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
> + ;
>
> - while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) {
> - timeout--;
> - if (timeout == 0)
> - break;
> - }
> + tmp = readl(&pmc->mckr);
> + tmp &= ~AT91_PMC_MCKR_MDIV_MASK;
> + tmp |= mckr & AT91_PMC_MCKR_MDIV_MASK;
> + writel(tmp, &pmc->mckr);
> + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
> + ;
> +
> + tmp = readl(&pmc->mckr);
> + tmp &= ~AT91_PMC_MCKR_PLLADIV_MASK;
> + tmp |= mckr & AT91_PMC_MCKR_PLLADIV_MASK;
> + writel(tmp, &pmc->mckr);
> + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
> + ;
> +
> + tmp = readl(&pmc->mckr);
> + tmp &= ~AT91_PMC_MCKR_CSS_MASK;
> + tmp |= mckr & AT91_PMC_MCKR_CSS_MASK;
> + writel(tmp, &pmc->mckr);
> + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
> + ;
> }
>
> void at91_periph_clk_enable(int id)
>
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply [flat|nested] 10+ messages in thread* [U-Boot] [PATCH 1/4] ARM: atmel: arm926ejs: fix clock configuration
2015-03-17 7:45 ` Heiko Schocher
@ 2015-03-17 7:58 ` Bo Shen
2015-03-17 8:10 ` Heiko Schocher
0 siblings, 1 reply; 10+ messages in thread
From: Bo Shen @ 2015-03-17 7:58 UTC (permalink / raw)
To: u-boot
Hi Heiko,
On 03/17/2015 03:45 PM, Heiko Schocher wrote:
> Hello Bo,
>
> Am 13.03.2015 10:19, schrieb Bo Shen:
>> Config MCKR according to the datasheet sequence, or else it
>> will cause the MCKR configuration failed.
>>
>> Remove timeout checking for clock configuration, if configure
>> the clock failed, let the system hang while not run in wrong
>> clock configuration.
>>
>> Signed-off-by: Bo Shen <voice.shen@atmel.com>
>> ---
>>
>> arch/arm/mach-at91/arm926ejs/clock.c | 54
>> +++++++++++++++++++-----------------
>> 1 file changed, 28 insertions(+), 26 deletions(-)
>
> Tested on the corvus and taurus board.
>
> Tested-by: Heiko Schocher <hs@denx.de>
Thanks.
>> diff --git a/arch/arm/mach-at91/arm926ejs/clock.c
>> b/arch/arm/mach-at91/arm926ejs/clock.c
>> index f363982..8d6934e 100644
>> --- a/arch/arm/mach-at91/arm926ejs/clock.c
>> +++ b/arch/arm/mach-at91/arm926ejs/clock.c
>> @@ -195,50 +195,52 @@ int at91_clock_init(unsigned long main_clock)
>> void at91_plla_init(u32 pllar)
>> {
>> struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
>> - int timeout = AT91_PLL_LOCK_TIMEOUT;
>>
>> writel(pllar, &pmc->pllar);
>> - while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY))) {
>> - timeout--;
>> - if (timeout == 0)
>> - break;
>> - }
>> + while (!(readl(&pmc->sr) & AT91_PMC_LOCKA))
>> + ;
>
> just hanging is maybe also bad ... could we hang with adding a
>
> if (timeout == 0) {
> debug("could not set PLL(A|B)\n");
> timeout = AT91_PLL_LOCK_TIMEOUT;
> }
>
> Thinking about it ... have we setup here the debug uart already?
> If not, forget my comment
Yes the uart is not ready. And one more thing, if the clock is not setup
correctly, then the system will run in abnormal status. So, I remove the
timeout check here.
Best Regards,
Bo Shen
> bye,
> Heiko
>> }
>> void at91_pllb_init(u32 pllbr)
>> {
>> struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
>> - int timeout = AT91_PLL_LOCK_TIMEOUT;
>>
>> writel(pllbr, &pmc->pllbr);
>> - while (!(readl(&pmc->sr) & (AT91_PMC_LOCKB | AT91_PMC_MCKRDY))) {
>> - timeout--;
>> - if (timeout == 0)
>> - break;
>> - }
>> + while (!(readl(&pmc->sr) & AT91_PMC_LOCKB))
>> + ;
>> }
>>
>> void at91_mck_init(u32 mckr)
>> {
>> struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
>> - int timeout = AT91_PLL_LOCK_TIMEOUT;
>> u32 tmp;
>>
>> tmp = readl(&pmc->mckr);
>> - tmp &= ~(AT91_PMC_MCKR_PRES_MASK |
>> - AT91_PMC_MCKR_MDIV_MASK |
>> - AT91_PMC_MCKR_PLLADIV_MASK |
>> - AT91_PMC_MCKR_CSS_MASK);
>> - tmp |= mckr & (AT91_PMC_MCKR_PRES_MASK |
>> - AT91_PMC_MCKR_MDIV_MASK |
>> - AT91_PMC_MCKR_PLLADIV_MASK |
>> - AT91_PMC_MCKR_CSS_MASK);
>> + tmp &= ~AT91_PMC_MCKR_PRES_MASK;
>> + tmp |= mckr & AT91_PMC_MCKR_PRES_MASK;
>> writel(tmp, &pmc->mckr);
>> + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
>> + ;
>>
>> - while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) {
>> - timeout--;
>> - if (timeout == 0)
>> - break;
>> - }
>> + tmp = readl(&pmc->mckr);
>> + tmp &= ~AT91_PMC_MCKR_MDIV_MASK;
>> + tmp |= mckr & AT91_PMC_MCKR_MDIV_MASK;
>> + writel(tmp, &pmc->mckr);
>> + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
>> + ;
>> +
>> + tmp = readl(&pmc->mckr);
>> + tmp &= ~AT91_PMC_MCKR_PLLADIV_MASK;
>> + tmp |= mckr & AT91_PMC_MCKR_PLLADIV_MASK;
>> + writel(tmp, &pmc->mckr);
>> + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
>> + ;
>> +
>> + tmp = readl(&pmc->mckr);
>> + tmp &= ~AT91_PMC_MCKR_CSS_MASK;
>> + tmp |= mckr & AT91_PMC_MCKR_CSS_MASK;
>> + writel(tmp, &pmc->mckr);
>> + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
>> + ;
>> }
>>
>> void at91_periph_clk_enable(int id)
>>
>
^ permalink raw reply [flat|nested] 10+ messages in thread* [U-Boot] [PATCH 1/4] ARM: atmel: arm926ejs: fix clock configuration
2015-03-17 7:58 ` Bo Shen
@ 2015-03-17 8:10 ` Heiko Schocher
0 siblings, 0 replies; 10+ messages in thread
From: Heiko Schocher @ 2015-03-17 8:10 UTC (permalink / raw)
To: u-boot
Hello Bo,
Am 17.03.2015 08:58, schrieb Bo Shen:
> Hi Heiko,
>
> On 03/17/2015 03:45 PM, Heiko Schocher wrote:
>> Hello Bo,
>>
>> Am 13.03.2015 10:19, schrieb Bo Shen:
>>> Config MCKR according to the datasheet sequence, or else it
>>> will cause the MCKR configuration failed.
>>>
>>> Remove timeout checking for clock configuration, if configure
>>> the clock failed, let the system hang while not run in wrong
>>> clock configuration.
>>>
>>> Signed-off-by: Bo Shen <voice.shen@atmel.com>
>>> ---
>>>
>>> arch/arm/mach-at91/arm926ejs/clock.c | 54
>>> +++++++++++++++++++-----------------
>>> 1 file changed, 28 insertions(+), 26 deletions(-)
>>
>> Tested on the corvus and taurus board.
>>
>> Tested-by: Heiko Schocher <hs@denx.de>
>
> Thanks.
>
>>> diff --git a/arch/arm/mach-at91/arm926ejs/clock.c
>>> b/arch/arm/mach-at91/arm926ejs/clock.c
>>> index f363982..8d6934e 100644
>>> --- a/arch/arm/mach-at91/arm926ejs/clock.c
>>> +++ b/arch/arm/mach-at91/arm926ejs/clock.c
>>> @@ -195,50 +195,52 @@ int at91_clock_init(unsigned long main_clock)
>>> void at91_plla_init(u32 pllar)
>>> {
>>> struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
>>> - int timeout = AT91_PLL_LOCK_TIMEOUT;
>>>
>>> writel(pllar, &pmc->pllar);
>>> - while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY))) {
>>> - timeout--;
>>> - if (timeout == 0)
>>> - break;
>>> - }
>>> + while (!(readl(&pmc->sr) & AT91_PMC_LOCKA))
>>> + ;
>>
>> just hanging is maybe also bad ... could we hang with adding a
>>
>> if (timeout == 0) {
>> debug("could not set PLL(A|B)\n");
>> timeout = AT91_PLL_LOCK_TIMEOUT;
>> }
>>
>> Thinking about it ... have we setup here the debug uart already?
>> If not, forget my comment
>
> Yes the uart is not ready. And one more thing, if the clock is not setup correctly, then the system will run in abnormal status. So, I remove the timeout check here.
Ok, thanks!
bye,
Heiko
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 2/4] ARM: atmel: at91sam9m10g45ek: enable spl support
2015-03-13 9:19 [U-Boot] [PATCH 0/4] ARM: atmel: boards: enable SPL support Bo Shen
2015-03-13 9:19 ` [U-Boot] [PATCH 1/4] ARM: atmel: arm926ejs: fix clock configuration Bo Shen
@ 2015-03-13 9:19 ` Bo Shen
2015-03-13 9:34 ` Masahiro Yamada
2015-03-13 9:19 ` [U-Boot] [PATCH 3/4] ARM: atmel: at91sam9x5ek: " Bo Shen
2015-03-13 9:19 ` [U-Boot] [PATCH 4/4] ARM: atmel: at91sam9n12ek: " Bo Shen
3 siblings, 1 reply; 10+ messages in thread
From: Bo Shen @ 2015-03-13 9:19 UTC (permalink / raw)
To: u-boot
Supports boot up from NAND flash with software ECC eanbled.
And supports boot up from SD/MMC card with FAT file system.
As the boot from SD/MMC card with FAT file system, the BSS
segment is too big to fit into SRAM, so, use the lds to put
it into SDRAM.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
---
arch/arm/mach-at91/Kconfig | 1 +
arch/arm/mach-at91/arm926ejs/u-boot-spl.lds | 48 +++++++++++++++
arch/arm/mach-at91/spl_at91.c | 6 +-
board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 80 +++++++++++++++++++++++++
configs/at91sam9m10g45ek_mmc_defconfig | 7 ++-
configs/at91sam9m10g45ek_nandflash_defconfig | 7 ++-
include/configs/at91sam9m10g45ek.h | 58 ++++++++++++++++++
7 files changed, 200 insertions(+), 7 deletions(-)
create mode 100644 arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 30945c1..25da926 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -66,6 +66,7 @@ config TARGET_STAMP9G20
config TARGET_AT91SAM9M10G45EK
bool "Atmel AT91SAM9M10G45-EK board"
select CPU_ARM926EJS
+ select SUPPORT_SPL
config TARGET_PM9G45
bool "Ronetix pm9g45 board"
diff --git a/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
new file mode 100644
index 0000000..acadd1d
--- /dev/null
+++ b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2015 Atmel Corporation
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE, \
+ LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+ LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ .text :
+ {
+ __start = .;
+ *(.vectors)
+ arch/arm/cpu/arm926ejs/start.o (.text*)
+ *(.text*)
+ } >.sram
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+
+ . = ALIGN(4);
+ .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+
+ . = ALIGN(4);
+ __image_copy_end = .;
+
+ .end :
+ {
+ *(.__end)
+ } >.sram
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_end = .;
+ } >.sdram
+}
diff --git a/arch/arm/mach-at91/spl_at91.c b/arch/arm/mach-at91/spl_at91.c
index 89f588b..af6fc0d 100644
--- a/arch/arm/mach-at91/spl_at91.c
+++ b/arch/arm/mach-at91/spl_at91.c
@@ -71,7 +71,11 @@ void __weak at91_spl_board_init(void)
{
}
-void spl_board_init(void)
+void __weak spl_board_init(void)
+{
+}
+
+void board_init_f(ulong dummy)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
index b807ef9..4289179 100644
--- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
+++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
@@ -8,6 +8,7 @@
#include <common.h>
#include <asm/io.h>
+#include <asm/arch/clk.h>
#include <asm/arch/at91sam9g45_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
@@ -15,6 +16,7 @@
#include <asm/arch/gpio.h>
#include <asm/arch/clk.h>
#include <lcd.h>
+#include <linux/mtd/nand.h>
#include <atmel_lcdc.h>
#include <atmel_mci.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
@@ -71,6 +73,84 @@ void at91sam9m10g45ek_nand_hw_init(void)
}
#endif
+#if defined(CONFIG_SPL_BUILD)
+#include <spl.h>
+#include <nand.h>
+
+void at91_spl_board_init(void)
+{
+ /*
+ * On the at91sam9m10g45ek board, the chip wm9711 stays in the
+ * test mode, so it needs do some action to exit test mode.
+ */
+ at91_periph_clk_enable(ATMEL_ID_PIODE);
+ at91_set_gpio_output(AT91_PIN_PD7, 0);
+ at91_set_gpio_output(AT91_PIN_PD8, 0);
+ at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1);
+ at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1);
+
+#ifdef CONFIG_SYS_USE_MMC
+ at91_mci_hw_init();
+#elif CONFIG_SYS_USE_NANDFLASH
+ at91sam9m10g45ek_nand_hw_init();
+#endif
+}
+
+#include <asm/arch/atmel_mpddrc.h>
+static void ddr2_conf(struct atmel_mpddr *ddr2)
+{
+ ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+ ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+ ATMEL_MPDDRC_CR_NR_ROW_14 |
+ ATMEL_MPDDRC_CR_DQMS_SHARED |
+ ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
+
+ ddr2->rtr = 0x24b;
+
+ ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
+ 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
+ 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
+ 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 60 ns */
+ 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
+ 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
+ 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
+ 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
+
+ ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
+ 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+ 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+ 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+ ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+ 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+ 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ struct atmel_mpddr ddr2;
+ unsigned long csa;
+
+ ddr2_conf(&ddr2);
+
+ /* enable DDR2 clock */
+ writel(0x4, &pmc->scer);
+
+ /* Chip select 1 is for DDR2/SDRAM */
+ csa = readl(&mat->ebicsa);
+ csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
+ csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V;
+ writel(csa, &mat->ebicsa);
+
+ /* DDRAM2 Controller initialize */
+ ddr2_init(ATMEL_BASE_CS6, &ddr2);
+}
+#endif
+
#ifdef CONFIG_CMD_USB
static void at91sam9m10g45ek_usb_hw_init(void)
{
diff --git a/configs/at91sam9m10g45ek_mmc_defconfig b/configs/at91sam9m10g45ek_mmc_defconfig
index 6949d3a..84d3133 100644
--- a/configs/at91sam9m10g45ek_mmc_defconfig
+++ b/configs/at91sam9m10g45ek_mmc_defconfig
@@ -1,4 +1,5 @@
+CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC"
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_AT91SAM9M10G45EK=y
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_AT91=y
++S:CONFIG_TARGET_AT91SAM9M10G45EK=y
diff --git a/configs/at91sam9m10g45ek_nandflash_defconfig b/configs/at91sam9m10g45ek_nandflash_defconfig
index 30967e3..5bcb0f7 100644
--- a/configs/at91sam9m10g45ek_nandflash_defconfig
+++ b/configs/at91sam9m10g45ek_nandflash_defconfig
@@ -1,4 +1,5 @@
+CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_NANDFLASH"
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_AT91SAM9M10G45EK=y
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_AT91=y
++S:CONFIG_TARGET_AT91SAM9M10G45EK=y
diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h
index db5d5ea..e4c49f4 100644
--- a/include/configs/at91sam9m10g45ek.h
+++ b/include/configs/at91sam9m10g45ek.h
@@ -203,4 +203,62 @@
*/
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
+/* Defines for SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE 0x300000
+#define CONFIG_SPL_MAX_SIZE 0x010000
+#define CONFIG_SPL_STACK 0x310000
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+
+#define CONFIG_SYS_MONITOR_LEN 0x80000
+
+#ifdef CONFIG_SYS_USE_MMC
+
+#define CONFIG_SPL_BSS_START_ADDR 0x70000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000
+#define CONFIG_SYS_SPL_MALLOC_START 0x70080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000
+
+#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+
+#elif CONFIG_SYS_USE_NANDFLASH
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_NAND_SOFTECC
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+
+#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
+#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
+#define CONFIG_SYS_NAND_PAGE_COUNT 64
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCSIZE 256
+#define CONFIG_SYS_NAND_ECCBYTES 3
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
+ 48, 49, 50, 51, 52, 53, 54, 55, \
+ 56, 57, 58, 59, 60, 61, 62, 63, }
+#endif
+
+#define CONFIG_SPL_ATMEL_SIZE
+#define CONFIG_SYS_MASTER_CLOCK 132096000
+#define CONFIG_SYS_AT91_PLLA 0x20c73f03
+#define CONFIG_SYS_MCKR 0x1301
+#define CONFIG_SYS_MCKR_CSS 0x1302
+
+#define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC0
#endif
--
2.3.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* [U-Boot] [PATCH 2/4] ARM: atmel: at91sam9m10g45ek: enable spl support
2015-03-13 9:19 ` [U-Boot] [PATCH 2/4] ARM: atmel: at91sam9m10g45ek: enable spl support Bo Shen
@ 2015-03-13 9:34 ` Masahiro Yamada
2015-03-13 9:36 ` Bo Shen
0 siblings, 1 reply; 10+ messages in thread
From: Masahiro Yamada @ 2015-03-13 9:34 UTC (permalink / raw)
To: u-boot
Hi Bo,
2015-03-13 18:19 GMT+09:00 Bo Shen <voice.shen@atmel.com>:
> diff --git a/configs/at91sam9m10g45ek_mmc_defconfig b/configs/at91sam9m10g45ek_mmc_defconfig
> index 6949d3a..84d3133 100644
> --- a/configs/at91sam9m10g45ek_mmc_defconfig
> +++ b/configs/at91sam9m10g45ek_mmc_defconfig
> @@ -1,4 +1,5 @@
> +CONFIG_SPL=y
> CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC"
> -CONFIG_ARM=y
> -CONFIG_ARCH_AT91=y
> -CONFIG_TARGET_AT91SAM9M10G45EK=y
> ++S:CONFIG_ARM=y
> ++S:CONFIG_ARCH_AT91=y
> ++S:CONFIG_TARGET_AT91SAM9M10G45EK=y
I abolished the prefixes such "+S".
Now they are harmless, but meaningless.
I am ripping off all of them:
http://patchwork.ozlabs.org/patch/449347/
Could you please not change those three lines?
--
Best Regards
Masahiro Yamada
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 2/4] ARM: atmel: at91sam9m10g45ek: enable spl support
2015-03-13 9:34 ` Masahiro Yamada
@ 2015-03-13 9:36 ` Bo Shen
0 siblings, 0 replies; 10+ messages in thread
From: Bo Shen @ 2015-03-13 9:36 UTC (permalink / raw)
To: u-boot
Hi Masahiro,
On 03/13/2015 05:34 PM, Masahiro Yamada wrote:
> Hi Bo,
>
>
> 2015-03-13 18:19 GMT+09:00 Bo Shen <voice.shen@atmel.com>:
>
>> diff --git a/configs/at91sam9m10g45ek_mmc_defconfig b/configs/at91sam9m10g45ek_mmc_defconfig
>> index 6949d3a..84d3133 100644
>> --- a/configs/at91sam9m10g45ek_mmc_defconfig
>> +++ b/configs/at91sam9m10g45ek_mmc_defconfig
>> @@ -1,4 +1,5 @@
>> +CONFIG_SPL=y
>> CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC"
>> -CONFIG_ARM=y
>> -CONFIG_ARCH_AT91=y
>> -CONFIG_TARGET_AT91SAM9M10G45EK=y
>> ++S:CONFIG_ARM=y
>> ++S:CONFIG_ARCH_AT91=y
>> ++S:CONFIG_TARGET_AT91SAM9M10G45EK=y
>
> I abolished the prefixes such "+S".
> Now they are harmless, but meaningless.
>
> I am ripping off all of them:
> http://patchwork.ozlabs.org/patch/449347/
>
> Could you please not change those three lines?
Thanks.
I will remove this change in next version.
Thanks again.
Best Regards,
Bo Shen
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 3/4] ARM: atmel: at91sam9x5ek: enable spl support
2015-03-13 9:19 [U-Boot] [PATCH 0/4] ARM: atmel: boards: enable SPL support Bo Shen
2015-03-13 9:19 ` [U-Boot] [PATCH 1/4] ARM: atmel: arm926ejs: fix clock configuration Bo Shen
2015-03-13 9:19 ` [U-Boot] [PATCH 2/4] ARM: atmel: at91sam9m10g45ek: enable spl support Bo Shen
@ 2015-03-13 9:19 ` Bo Shen
2015-03-13 9:19 ` [U-Boot] [PATCH 4/4] ARM: atmel: at91sam9n12ek: " Bo Shen
3 siblings, 0 replies; 10+ messages in thread
From: Bo Shen @ 2015-03-13 9:19 UTC (permalink / raw)
To: u-boot
Enable SPL support for at91sam9x5ek board. Now, it supports
boot up from NAND flash and SPI flash.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
---
arch/arm/mach-at91/Kconfig | 1 +
arch/arm/mach-at91/Makefile | 1 +
arch/arm/mach-at91/include/mach/at91_pmc.h | 6 ++-
arch/arm/mach-at91/include/mach/at91sam9x5.h | 10 ++++
arch/arm/mach-at91/mpddrc.c | 3 +-
arch/arm/mach-at91/spl.c | 2 +-
arch/arm/mach-at91/spl_at91.c | 5 ++
board/atmel/at91sam9x5ek/at91sam9x5ek.c | 74 ++++++++++++++++++++++++++++
configs/at91sam9x5ek_nandflash_defconfig | 7 +--
configs/at91sam9x5ek_spiflash_defconfig | 7 +--
include/configs/at91sam9x5ek.h | 57 +++++++++++++++++++++
11 files changed, 163 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 25da926..bdf87f9 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -83,6 +83,7 @@ config TARGET_AT91SAM9RLEK
config TARGET_AT91SAM9X5EK
bool "Atmel AT91SAM9X5-EK board"
select CPU_ARM926EJS
+ select SUPPORT_SPL
config TARGET_SAMA5D3_XPLAINED
bool "SAMA5D3 Xplained board"
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index e596ba6..ba83616 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -2,6 +2,7 @@ obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o
ifneq ($(CONFIG_SPL_BUILD),)
obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o
obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o
+obj-$(CONFIG_AT91SAM9X5) += mpddrc.o spl_at91.o
obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o
obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o
obj-y += spl.o
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index 65691ab..c903260 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -97,7 +97,8 @@ typedef struct at91_pmc {
#define AT91_PMC_MCKR_CSS_PLLB 0x00000003
#define AT91_PMC_MCKR_CSS_MASK 0x00000003
-#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
+#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
+ defined(CONFIG_AT91SAM9X5)
#define AT91_PMC_MCKR_PRES_1 0x00000000
#define AT91_PMC_MCKR_PRES_2 0x00000010
#define AT91_PMC_MCKR_PRES_4 0x00000020
@@ -126,7 +127,8 @@ typedef struct at91_pmc {
#else
#define AT91_PMC_MCKR_MDIV_1 0x00000000
#define AT91_PMC_MCKR_MDIV_2 0x00000100
-#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
+#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
+ defined(CONFIG_AT91SAM9X5)
#define AT91_PMC_MCKR_MDIV_3 0x00000300
#endif
#define AT91_PMC_MCKR_MDIV_4 0x00000200
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
index 36a5cdf..d18c936 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
@@ -124,6 +124,16 @@
#define ATMEL_BASE_EHCI 0x00700000 /* USB Host controller (EHCI) */
#endif
+/*
+ * External memory
+ */
+#define ATMEL_BASE_CS0 0x10000000
+#define ATMEL_BASE_CS1 0x20000000
+#define ATMEL_BASE_CS2 0x30000000
+#define ATMEL_BASE_CS3 0x40000000
+#define ATMEL_BASE_CS4 0x50000000
+#define ATMEL_BASE_CS5 0x60000000
+
/* 9x5 series chip id definitions */
#define ARCH_ID_AT91SAM9X5 0x819a05a0
#define ARCH_ID_VERSION_MASK 0x1f
diff --git a/arch/arm/mach-at91/mpddrc.c b/arch/arm/mach-at91/mpddrc.c
index beec13d..24d5fcd 100644
--- a/arch/arm/mach-at91/mpddrc.c
+++ b/arch/arm/mach-at91/mpddrc.c
@@ -19,7 +19,8 @@ static inline void atmel_mpddr_op(int mode, u32 ram_address)
static int ddr2_decodtype_is_seq(u32 cr)
{
-#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
+#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
+ defined(CONFIG_AT91SAM9X5)
if (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED)
return 0;
#endif
diff --git a/arch/arm/mach-at91/spl.c b/arch/arm/mach-at91/spl.c
index aaa5eec..27a405a 100644
--- a/arch/arm/mach-at91/spl.c
+++ b/arch/arm/mach-at91/spl.c
@@ -29,7 +29,7 @@ u32 spl_boot_device(void)
return BOOT_DEVICE_MMC1;
#elif CONFIG_SYS_USE_NANDFLASH
return BOOT_DEVICE_NAND;
-#elif CONFIG_SYS_USE_SERIALFLASH
+#elif CONFIG_SYS_USE_SERIALFLASH || CONFIG_SYS_USE_SPIFLASH
return BOOT_DEVICE_SPI;
#endif
return BOOT_DEVICE_NONE;
diff --git a/arch/arm/mach-at91/spl_at91.c b/arch/arm/mach-at91/spl_at91.c
index af6fc0d..e28e568 100644
--- a/arch/arm/mach-at91/spl_at91.c
+++ b/arch/arm/mach-at91/spl_at91.c
@@ -115,9 +115,14 @@ void board_init_f(ulong dummy)
timer_init();
/* enable clocks for all PIOs */
+#ifdef CONFIG_AT91SAM9X5
+ at91_periph_clk_enable(ATMEL_ID_PIOAB);
+ at91_periph_clk_enable(ATMEL_ID_PIOCD);
+#else
at91_periph_clk_enable(ATMEL_ID_PIOA);
at91_periph_clk_enable(ATMEL_ID_PIOB);
at91_periph_clk_enable(ATMEL_ID_PIOC);
+#endif
/* init console */
at91_seriald_hw_init();
preloader_console_init();
diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
index 17a2a40..114ac5c 100644
--- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c
+++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
@@ -293,3 +293,77 @@ int dram_init(void)
CONFIG_SYS_SDRAM_SIZE);
return 0;
}
+
+#if defined(CONFIG_SPL_BUILD)
+#include <spl.h>
+#include <nand.h>
+
+void at91_spl_board_init(void)
+{
+#ifdef CONFIG_SYS_USE_MMC
+ at91_mci_hw_init();
+#elif CONFIG_SYS_USE_NANDFLASH
+ at91sam9x5ek_nand_hw_init();
+#elif CONFIG_SYS_USE_SPIFLASH
+ at91_spi0_hw_init(1 << 4);
+#endif
+}
+
+#include <asm/arch/atmel_mpddrc.h>
+static void ddr2_conf(struct atmel_mpddr *ddr2)
+{
+ ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+ ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+ ATMEL_MPDDRC_CR_NR_ROW_13 |
+ ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+ ATMEL_MPDDRC_CR_NB_8BANKS |
+ ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);
+
+ ddr2->rtr = 0x411;
+
+ ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
+ 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
+
+ ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
+ 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+ 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+ 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+ ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+ 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+ 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ struct atmel_mpddr ddr2;
+ unsigned long csa;
+
+ ddr2_conf(&ddr2);
+
+ /* enable DDR2 clock */
+ writel(0x4, &pmc->scer);
+
+ /* Chip select 1 is for DDR2/SDRAM */
+ csa = readl(&matrix->ebicsa);
+ csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
+ csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
+ csa |= AT91_MATRIX_EBI_DBPD_OFF;
+ csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
+ writel(csa, &matrix->ebicsa);
+
+ /* DDRAM2 Controller initialize */
+ ddr2_init(ATMEL_BASE_CS1, &ddr2);
+}
+#endif
diff --git a/configs/at91sam9x5ek_nandflash_defconfig b/configs/at91sam9x5ek_nandflash_defconfig
index c2ebb00..2303cb4 100644
--- a/configs/at91sam9x5ek_nandflash_defconfig
+++ b/configs/at91sam9x5ek_nandflash_defconfig
@@ -1,4 +1,5 @@
+CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_NANDFLASH"
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_AT91SAM9X5EK=y
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_AT91=y
++S:CONFIG_TARGET_AT91SAM9X5EK=y
diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig
index 76f68a6..538f0c1 100644
--- a/configs/at91sam9x5ek_spiflash_defconfig
+++ b/configs/at91sam9x5ek_spiflash_defconfig
@@ -1,4 +1,5 @@
+CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_SPIFLASH"
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_AT91SAM9X5EK=y
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_AT91=y
++S:CONFIG_TARGET_AT91SAM9X5EK=y
diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h
index 6d8b71d..1a481b3 100644
--- a/include/configs/at91sam9x5ek.h
+++ b/include/configs/at91sam9x5ek.h
@@ -243,4 +243,61 @@
*/
#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000)
+/* SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE 0x300000
+#define CONFIG_SPL_MAX_SIZE 0x6000
+#define CONFIG_SPL_STACK 0x308000
+
+#define CONFIG_SPL_BSS_START_ADDR 0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
+#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SYS_MONITOR_LEN (512 << 10)
+
+#define CONFIG_SYS_MASTER_CLOCK 132096000
+#define CONFIG_SYS_AT91_PLLA 0x20c73f03
+#define CONFIG_SYS_MCKR 0x1301
+#define CONFIG_SYS_MCKR_CSS 0x1302
+
+#define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC
+
+#ifdef CONFIG_SYS_USE_MMC
+#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+
+#elif CONFIG_SYS_USE_NANDFLASH
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
+#define CONFIG_SYS_NAND_PAGE_COUNT 64
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
+#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
+
+#elif CONFIG_SYS_USE_SPIFLASH
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400
+
+#endif
+
#endif
--
2.3.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* [U-Boot] [PATCH 4/4] ARM: atmel: at91sam9n12ek: enable spl support
2015-03-13 9:19 [U-Boot] [PATCH 0/4] ARM: atmel: boards: enable SPL support Bo Shen
` (2 preceding siblings ...)
2015-03-13 9:19 ` [U-Boot] [PATCH 3/4] ARM: atmel: at91sam9x5ek: " Bo Shen
@ 2015-03-13 9:19 ` Bo Shen
3 siblings, 0 replies; 10+ messages in thread
From: Bo Shen @ 2015-03-13 9:19 UTC (permalink / raw)
To: u-boot
Enable SPL support for at91sam9n12ek boards, now it supports
boot up from NAND flash, serial flash.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
---
arch/arm/mach-at91/Kconfig | 1 +
arch/arm/mach-at91/Makefile | 1 +
arch/arm/mach-at91/include/mach/at91_pmc.h | 4 +-
arch/arm/mach-at91/mpddrc.c | 2 +-
arch/arm/mach-at91/spl_at91.c | 2 +-
board/atmel/at91sam9n12ek/at91sam9n12ek.c | 73 ++++++++++++++++++++++++++++++
configs/at91sam9n12ek_nandflash_defconfig | 7 +--
configs/at91sam9n12ek_spiflash_defconfig | 7 +--
include/configs/at91sam9n12ek.h | 58 +++++++++++++++++++++++-
9 files changed, 144 insertions(+), 11 deletions(-)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index bdf87f9..30c4e17 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -75,6 +75,7 @@ config TARGET_PM9G45
config TARGET_AT91SAM9N12EK
bool "Atmel AT91SAM9N12-EK board"
select CPU_ARM926EJS
+ select SUPPORT_SPL
config TARGET_AT91SAM9RLEK
bool "Atmel at91sam9rl reference board"
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index ba83616..0d3ee48 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -2,6 +2,7 @@ obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o
ifneq ($(CONFIG_SPL_BUILD),)
obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o
obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o
+obj-$(CONFIG_AT91SAM9N12) += mpddrc.o spl_at91.o
obj-$(CONFIG_AT91SAM9X5) += mpddrc.o spl_at91.o
obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o
obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index c903260..ebb7dec 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -98,7 +98,7 @@ typedef struct at91_pmc {
#define AT91_PMC_MCKR_CSS_MASK 0x00000003
#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
- defined(CONFIG_AT91SAM9X5)
+ defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
#define AT91_PMC_MCKR_PRES_1 0x00000000
#define AT91_PMC_MCKR_PRES_2 0x00000010
#define AT91_PMC_MCKR_PRES_4 0x00000020
@@ -128,7 +128,7 @@ typedef struct at91_pmc {
#define AT91_PMC_MCKR_MDIV_1 0x00000000
#define AT91_PMC_MCKR_MDIV_2 0x00000100
#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
- defined(CONFIG_AT91SAM9X5)
+ defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
#define AT91_PMC_MCKR_MDIV_3 0x00000300
#endif
#define AT91_PMC_MCKR_MDIV_4 0x00000200
diff --git a/arch/arm/mach-at91/mpddrc.c b/arch/arm/mach-at91/mpddrc.c
index 24d5fcd..e2b6a49 100644
--- a/arch/arm/mach-at91/mpddrc.c
+++ b/arch/arm/mach-at91/mpddrc.c
@@ -20,7 +20,7 @@ static inline void atmel_mpddr_op(int mode, u32 ram_address)
static int ddr2_decodtype_is_seq(u32 cr)
{
#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
- defined(CONFIG_AT91SAM9X5)
+ defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
if (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED)
return 0;
#endif
diff --git a/arch/arm/mach-at91/spl_at91.c b/arch/arm/mach-at91/spl_at91.c
index e28e568..a79a9dc 100644
--- a/arch/arm/mach-at91/spl_at91.c
+++ b/arch/arm/mach-at91/spl_at91.c
@@ -115,7 +115,7 @@ void board_init_f(ulong dummy)
timer_init();
/* enable clocks for all PIOs */
-#ifdef CONFIG_AT91SAM9X5
+#if defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
at91_periph_clk_enable(ATMEL_ID_PIOAB);
at91_periph_clk_enable(ATMEL_ID_PIOCD);
#else
diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
index 9adc992..4f46a03 100644
--- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c
+++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
@@ -257,3 +257,76 @@ int dram_init(void)
CONFIG_SYS_SDRAM_SIZE);
return 0;
}
+
+#if defined(CONFIG_SPL_BUILD)
+#include <spl.h>
+#include <nand.h>
+
+void at91_spl_board_init(void)
+{
+#ifdef CONFIG_SYS_USE_MMC
+ at91_mci_hw_init();
+#elif CONFIG_SYS_USE_NANDFLASH
+ at91sam9n12ek_nand_hw_init();
+#elif CONFIG_SYS_USE_SPIFLASH
+ at91_spi0_hw_init(1 << 4);
+#endif
+}
+
+#include <asm/arch/atmel_mpddrc.h>
+static void ddr2_conf(struct atmel_mpddr *ddr2)
+{
+ ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+ ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+ ATMEL_MPDDRC_CR_NR_ROW_13 |
+ ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+ ATMEL_MPDDRC_CR_NB_8BANKS |
+ ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);
+
+ ddr2->rtr = 0x411;
+
+ ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
+ 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
+
+ ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
+ 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+ 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+ 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+ ddr2->tpr2 = (2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+ 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+ 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ struct atmel_mpddr ddr2;
+ unsigned long csa;
+
+ ddr2_conf(&ddr2);
+
+ /* enable DDR2 clock */
+ writel(0x4, &pmc->scer);
+
+ /* Chip select 1 is for DDR2/SDRAM */
+ csa = readl(&matrix->ebicsa);
+ csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
+ csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
+ csa |= AT91_MATRIX_EBI_DBPD_OFF;
+ csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
+ writel(csa, &matrix->ebicsa);
+
+ /* DDRAM2 Controller initialize */
+ ddr2_init(ATMEL_BASE_CS1, &ddr2);
+}
+#endif
diff --git a/configs/at91sam9n12ek_nandflash_defconfig b/configs/at91sam9n12ek_nandflash_defconfig
index f908246..8d003ef 100644
--- a/configs/at91sam9n12ek_nandflash_defconfig
+++ b/configs/at91sam9n12ek_nandflash_defconfig
@@ -1,4 +1,5 @@
+CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_NANDFLASH"
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_AT91SAM9N12EK=y
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_AT91=y
++S:CONFIG_TARGET_AT91SAM9N12EK=y
diff --git a/configs/at91sam9n12ek_spiflash_defconfig b/configs/at91sam9n12ek_spiflash_defconfig
index d106b5a..cddebe7 100644
--- a/configs/at91sam9n12ek_spiflash_defconfig
+++ b/configs/at91sam9n12ek_spiflash_defconfig
@@ -1,4 +1,5 @@
+CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_SPIFLASH"
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_AT91SAM9N12EK=y
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_AT91=y
++S:CONFIG_TARGET_AT91SAM9N12EK=y
diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h
index f02fce9..aeec8b8 100644
--- a/include/configs/at91sam9n12ek.h
+++ b/include/configs/at91sam9n12ek.h
@@ -228,6 +228,62 @@
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
-#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
+
+/* SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE 0x300000
+#define CONFIG_SPL_MAX_SIZE 0x6000
+#define CONFIG_SPL_STACK 0x308000
+
+#define CONFIG_SPL_BSS_START_ADDR 0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
+#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SYS_MONITOR_LEN (512 << 10)
+
+#define CONFIG_SYS_MASTER_CLOCK 132096000
+#define CONFIG_SYS_AT91_PLLA 0x20953f03
+#define CONFIG_SYS_MCKR 0x1301
+#define CONFIG_SYS_MCKR_CSS 0x1302
+
+#define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC
+
+#ifdef CONFIG_SYS_USE_MMC
+#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+
+#elif CONFIG_SYS_USE_NANDFLASH
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
+#define CONFIG_SYS_NAND_PAGE_COUNT 64
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
+#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
+
+#elif CONFIG_SYS_USE_SPIFLASH
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400
+
+#endif
#endif
--
2.3.0
^ permalink raw reply related [flat|nested] 10+ messages in thread