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From: Marc Zyngier <marc.zyngier@arm.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 4/6] armv8/mmu: Set bits marked RES1 in TCR
Date: Fri, 20 Mar 2015 18:16:44 +0000	[thread overview]
Message-ID: <550C640C.3020203@arm.com> (raw)
In-Reply-To: <1426852073-10299-4-git-send-email-thierry.reding@gmail.com>

On 20/03/15 11:47, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> For EL3 and EL2, the documentation says that bits 31 and 23 are reserved
> but should be written as 1.
> 
> For EL1, only bit 23 is not reserved, so only write bit 31 as 1.
> 
> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
> Cc: Marc Zyngier <marc.zyngier@arm.com>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  arch/arm/cpu/armv8/cache_v8.c    | 6 +++---
>  arch/arm/include/asm/armv8/mmu.h | 4 ++++
>  2 files changed, 7 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
> index 254a629a3b8c..f9b04057f696 100644
> --- a/arch/arm/cpu/armv8/cache_v8.c
> +++ b/arch/arm/cpu/armv8/cache_v8.c
> @@ -50,15 +50,15 @@ static void mmu_setup(void)
>  	el = current_el();
>  	if (el == 1) {
>  		set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
> -				  TCR_FLAGS | TCR_EL1_IPS_BITS,
> +				  TCR_EL1_RSVD | TCR_FLAGS | TCR_EL1_IPS_BITS,
>  				  MEMORY_ATTRIBUTES);
>  	} else if (el == 2) {
>  		set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
> -				  TCR_FLAGS | TCR_EL2_IPS_BITS,
> +				  TCR_EL2_RSVD | TCR_FLAGS | TCR_EL2_IPS_BITS,
>  				  MEMORY_ATTRIBUTES);
>  	} else {
>  		set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
> -				  TCR_FLAGS | TCR_EL3_IPS_BITS,
> +				  TCR_EL3_RSVD | TCR_FLAGS | TCR_EL3_IPS_BITS,
>  				  MEMORY_ATTRIBUTES);
>  	}
>  	/* enable the mmu */
> diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
> index 6d42f5533a74..8e577b34e4ba 100644
> --- a/arch/arm/include/asm/armv8/mmu.h
> +++ b/arch/arm/include/asm/armv8/mmu.h
> @@ -109,6 +109,10 @@
>  				TCR_IRGN_WBWA |		\
>  				TCR_T0SZ(VA_BITS))
>  
> +#define TCR_EL1_RSVD		(1 << 31)
> +#define TCR_EL2_RSVD		(1 << 31 | 1 << 23)
> +#define TCR_EL3_RSVD		(1 << 31 | 1 << 23)
> +
>  #ifndef __ASSEMBLY__
>  void set_pgtable_section(u64 *page_table, u64 index,
>  			 u64 section, u64 memory_type);
> 

Acked-by: Marc Zyngier <marc.zyngier@arm.com>

	M.
-- 
Jazz is not dead. It just smells funny...

  reply	other threads:[~2015-03-20 18:16 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-03-20 11:47 [U-Boot] [PATCH 1/6] armv8/cache: Fix page table creation Thierry Reding
2015-03-20 11:47 ` [U-Boot] [PATCH 2/6] armv8: Implement CONFIG_SYS_MALLOC_F_LEN support Thierry Reding
2015-03-24 14:47   ` FengHua
2015-03-20 11:47 ` [U-Boot] [PATCH 3/6] armv8/mmu: Clean up TCR programming Thierry Reding
2015-03-20 18:13   ` Marc Zyngier
2015-07-02 21:06     ` Albert ARIBAUD
2015-07-03  7:28       ` Marc Zyngier
2015-03-24 14:55   ` FengHua
2015-03-20 11:47 ` [U-Boot] [PATCH 4/6] armv8/mmu: Set bits marked RES1 in TCR Thierry Reding
2015-03-20 18:16   ` Marc Zyngier [this message]
2015-03-24 15:10   ` FengHua
2015-03-20 11:47 ` [U-Boot] [PATCH 5/6] armv8/gic: Fix GIC v2 initialization Thierry Reding
2015-03-20 18:03   ` Marc Zyngier
2015-03-20 11:47 ` [U-Boot] [PATCH 6/6] armv8: Allow SoCs to override the generic timer Thierry Reding
2015-03-20 18:18   ` Marc Zyngier
2015-03-24 14:59   ` FengHua
2015-03-20 18:06 ` [U-Boot] [PATCH 1/6] armv8/cache: Fix page table creation Marc Zyngier
2015-03-24 14:52 ` FengHua
2015-04-16 11:24 ` Albert ARIBAUD
2015-06-03 15:09   ` Albert ARIBAUD

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