[U-Boot] [PATCH 0/3] sunxi: Yones Toptech BD1078 support

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* [U-Boot] [PATCH 0/3] sunxi: Yones Toptech BD1078 support
@ 2015-03-22 17:12 Paul Kocialkowski
  2015-03-22 17:12 ` [U-Boot] [PATCH 1/3] sunxi: GPIO pin mux hardware-feature-specific function index defines Paul Kocialkowski
                   ` (4 more replies)
  0 siblings, 5 replies; 7+ messages in thread
From: Paul Kocialkowski @ 2015-03-22 17:12 UTC (permalink / raw)
  To: u-boot

This series goes on top of my previous series that concludes with Ainol AW1
support.

Also, if you're interested by the idea of using sunxi_name_to_gpio_bank, this
could be extended for UART as well, where *many* different pin mux setups are
possible. We are just lucky that hardware designers usually use the ports that
U-Boot selects, but there is no fundamental reason for that.

^ permalink raw reply	[flat|nested] 7+ messages in thread

* [U-Boot] [PATCH 1/3] sunxi: GPIO pin mux hardware-feature-specific function index defines
  2015-03-22 17:12 [U-Boot] [PATCH 0/3] sunxi: Yones Toptech BD1078 support Paul Kocialkowski
@ 2015-03-22 17:12 ` Paul Kocialkowski
  2015-03-22 17:12 ` [U-Boot] [PATCH 2/3] sunxi: Complete mmc pin mux for each supported platform, configured with Kconfig Paul Kocialkowski
                   ` (3 subsequent siblings)
  4 siblings, 0 replies; 7+ messages in thread
From: Paul Kocialkowski @ 2015-03-22 17:12 UTC (permalink / raw)
  To: u-boot

Each hardware feature exposed through the GPIO pin mux is usually using the same
function index (for a given port), so there is no need to define one value per
pin: one value per hardware feature per port is sufficient, avoids duplication
and makes everything easier to understand.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
---
 arch/arm/cpu/armv7/sunxi/board.c       | 29 +++++++++-------
 arch/arm/cpu/armv7/sunxi/rsb.c         |  8 ++---
 arch/arm/include/asm/arch-sunxi/gpio.h | 60 +++++++++++-----------------------
 board/sunxi/board.c                    | 12 +++----
 board/sunxi/gmac.c                     | 22 ++++++-------
 drivers/net/sunxi_emac.c               |  2 +-
 drivers/video/sunxi_display.c          |  8 ++---
 7 files changed, 62 insertions(+), 79 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index c02c015..c1b4cf5 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -46,28 +46,33 @@ static int gpio_init(void)
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
 #endif
-	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF2_UART0_TX);
-	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF4_UART0_RX);
+#if defined(CONFIG_MACH_SUN8I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0_TX);
+	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0_RX);
+#else
+	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0_TX);
+	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0_RX);
+#endif
 	sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
 #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I))
-	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
-	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
 	sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
-	sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
-	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
 	sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
-	sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH20_UART0_TX);
-	sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH21_UART0_RX);
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
 	sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
-	sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
-	sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
+	sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
+	sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
 	sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
 #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
-	sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL2_R_UART_TX);
-	sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL3_R_UART_RX);
+	sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
+	sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
 	sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
 #else
 #error Unsupported console port number. Please fix pin mux settings in board.c
diff --git a/arch/arm/cpu/armv7/sunxi/rsb.c b/arch/arm/cpu/armv7/sunxi/rsb.c
index b00befb..f115a9c 100644
--- a/arch/arm/cpu/armv7/sunxi/rsb.c
+++ b/arch/arm/cpu/armv7/sunxi/rsb.c
@@ -21,15 +21,15 @@ static int rsb_set_device_mode(void);
 static void rsb_cfg_io(void)
 {
 #ifdef CONFIG_MACH_SUN8I
-	sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL0_R_RSB_SCK);
-	sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL1_R_RSB_SDA);
+	sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB);
+	sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB);
 	sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
 	sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
 	sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
 	sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
 #elif defined CONFIG_MACH_SUN9I
-	sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN0_R_RSB_SCK);
-	sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN1_R_RSB_SDA);
+	sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB);
+	sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB);
 	sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
 	sunxi_gpio_set_pull(SUNXI_GPN(1), 1);
 	sunxi_gpio_set_drv(SUNXI_GPN(0), 2);
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index 3a4b8c3..a6b15d6 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -142,59 +142,37 @@ enum sunxi_gpio_number {
 #define SUNXI_GPIO_INPUT	0
 #define SUNXI_GPIO_OUTPUT	1
 
-#define SUNXI_GPA0_EMAC		2
-#define SUN6I_GPA0_GMAC		2
-#define SUN7I_GPA0_GMAC		5
+#define SUNXI_GPA_EMAC		2
+#define SUN6I_GPA_GMAC		2
+#define SUN7I_GPA_GMAC		5
 
-#define SUNXI_GPB0_TWI0		2
+#define SUNXI_GPB_TWI0		2
+#define SUN4I_GPB_UART0		2
+#define SUN5I_GPB_UART0		2
 
-#define SUN4I_GPB22_UART0_TX	2
-#define SUN4I_GPB23_UART0_RX	2
+#define SUNXI_GPC_SDC2		3
 
-#define SUN5I_GPB19_UART0_TX	2
-#define SUN5I_GPB20_UART0_RX	2
+#define SUNXI_GPD_LCD0		2
+#define SUNXI_GPD_LVDS0		3
 
-#define SUNXI_GPC6_SDC2		3
+#define SUNXI_GPF_SDC0		2
+#define SUNXI_GPF_UART0		4
+#define SUN8I_GPF_UART0		3
 
-#define SUNXI_GPD0_LCD0		2
-#define SUNXI_GPD0_LVDS0	3
+#define SUN5I_GPG_SDC1		2
+#define SUN5I_GPG_UART1		4
 
-#define SUNXI_GPF0_SDC0		2
+#define SUN6I_GPH_UART0		2
 
-#define SUNXI_GPF2_SDC0		2
-
-#ifdef CONFIG_MACH_SUN8I
-#define SUNXI_GPF2_UART0_TX	3
-#define SUNXI_GPF4_UART0_RX	3
-#else
-#define SUNXI_GPF2_UART0_TX	4
-#define SUNXI_GPF4_UART0_RX	4
-#endif
-
-#define SUN4I_GPG0_SDC1		4
-
-#define SUN5I_GPG3_SDC1		2
-
-#define SUN5I_GPG3_UART1_TX	4
-#define SUN5I_GPG4_UART1_RX	4
-
-#define SUN4I_GPH22_SDC1	5
-
-#define SUN6I_GPH20_UART0_TX	2
-#define SUN6I_GPH21_UART0_RX	2
-
-#define SUN4I_GPI4_SDC3		2
+#define SUN4I_GPI_SDC3		2
 
 #define SUN6I_GPL0_R_P2WI_SCK	3
 #define SUN6I_GPL1_R_P2WI_SDA	3
 
-#define SUN8I_GPL0_R_RSB_SCK	2
-#define SUN8I_GPL1_R_RSB_SDA	2
-#define SUN8I_GPL2_R_UART_TX	2
-#define SUN8I_GPL3_R_UART_RX	2
+#define SUN8I_GPL_R_RSB		2
+#define SUN8I_GPL_R_UART	2
 
-#define SUN9I_GPN0_R_RSB_SCK	3
-#define SUN9I_GPN1_R_RSB_SDA	3
+#define SUN9I_GPN_R_RSB		3
 
 /* GPIO pin pull-up/down config */
 #define SUNXI_GPIO_PULL_DISABLE	0
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index becdc8b..3af3973 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -76,7 +76,7 @@ static void mmc_pinmux_setup(int sdc)
 	case 0:
 		/* D1-PF0, D0-PF1, CLK-PF2, CMD-PF3, D3-PF4, D4-PF5 */
 		for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
-			sunxi_gpio_set_cfgpin(pin, SUNXI_GPF0_SDC0);
+			sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
 			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 			sunxi_gpio_set_drv(pin, 2);
 		}
@@ -85,7 +85,7 @@ static void mmc_pinmux_setup(int sdc)
 	case 1:
 		/* CMD-PG3, CLK-PG4, D0~D3-PG5-8 */
 		for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
-			sunxi_gpio_set_cfgpin(pin, SUN5I_GPG3_SDC1);
+			sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
 			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 			sunxi_gpio_set_drv(pin, 2);
 		}
@@ -94,7 +94,7 @@ static void mmc_pinmux_setup(int sdc)
 	case 2:
 		/* CMD-PC6, CLK-PC7, D0-PC8, D1-PC9, D2-PC10, D3-PC11 */
 		for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
-			sunxi_gpio_set_cfgpin(pin, SUNXI_GPC6_SDC2);
+			sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
 			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 			sunxi_gpio_set_drv(pin, 2);
 		}
@@ -103,7 +103,7 @@ static void mmc_pinmux_setup(int sdc)
 	case 3:
 		/* CMD-PI4, CLK-PI5, D0~D3-PI6~9 : 2 */
 		for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
-			sunxi_gpio_set_cfgpin(pin, SUN4I_GPI4_SDC3);
+			sunxi_gpio_set_cfgpin(pin, SUN4I_GPI_SDC3);
 			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 			sunxi_gpio_set_drv(pin, 2);
 		}
@@ -155,8 +155,8 @@ int board_mmc_init(bd_t *bis)
 
 void i2c_init_board(void)
 {
-	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUNXI_GPB0_TWI0);
-	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUNXI_GPB0_TWI0);
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUNXI_GPB_TWI0);
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUNXI_GPB_TWI0);
 	clock_twi_onoff(0, 1);
 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
 	soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c
index 8849132..63a7360 100644
--- a/board/sunxi/gmac.c
+++ b/board/sunxi/gmac.c
@@ -39,45 +39,45 @@ int sunxi_gmac_initialize(bd_t *bis)
 		if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
 			continue;
 #endif
-		sunxi_gpio_set_cfgpin(pin, SUN7I_GPA0_GMAC);
+		sunxi_gpio_set_cfgpin(pin, SUN7I_GPA_GMAC);
 		sunxi_gpio_set_drv(pin, 3);
 	}
 #elif defined CONFIG_RGMII
 	/* Configure sun6i RGMII mode pin mux settings */
 	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) {
-		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
 		sunxi_gpio_set_drv(pin, 3);
 	}
 	for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
-		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
 		sunxi_gpio_set_drv(pin, 3);
 	}
 	for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(20); pin++) {
-		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
 		sunxi_gpio_set_drv(pin, 3);
 	}
 	for (pin = SUNXI_GPA(25); pin <= SUNXI_GPA(27); pin++) {
-		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
 		sunxi_gpio_set_drv(pin, 3);
 	}
 #elif defined CONFIG_GMII
 	/* Configure sun6i GMII mode pin mux settings */
 	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(27); pin++) {
-		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
 		sunxi_gpio_set_drv(pin, 2);
 	}
 #else
 	/* Configure sun6i MII mode pin mux settings */
 	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++)
-		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
 	for (pin = SUNXI_GPA(8); pin <= SUNXI_GPA(9); pin++)
-		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
 	for (pin = SUNXI_GPA(11); pin <= SUNXI_GPA(14); pin++)
-		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
 	for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(24); pin++)
-		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
 	for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++)
-		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
 #endif
 
 #ifdef CONFIG_RGMII
diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c
index 5a06d68..2a9fd56 100644
--- a/drivers/net/sunxi_emac.c
+++ b/drivers/net/sunxi_emac.c
@@ -497,7 +497,7 @@ int sunxi_emac_initialize(void)
 
 	/* Configure pin mux settings for MII Ethernet */
 	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++)
-		sunxi_gpio_set_cfgpin(pin, SUNXI_GPA0_EMAC);
+		sunxi_gpio_set_cfgpin(pin, SUNXI_GPA_EMAC);
 
 	/* Set up clock gating */
 	setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_EMAC);
diff --git a/drivers/video/sunxi_display.c b/drivers/video/sunxi_display.c
index 4e12150..d2341b0 100644
--- a/drivers/video/sunxi_display.c
+++ b/drivers/video/sunxi_display.c
@@ -665,10 +665,10 @@ static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode,
 
 	for (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(27); pin++)
 #ifdef CONFIG_VIDEO_LCD_IF_PARALLEL
-		sunxi_gpio_set_cfgpin(pin, SUNXI_GPD0_LCD0);
+		sunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LCD0);
 #endif
 #ifdef CONFIG_VIDEO_LCD_IF_LVDS
-		sunxi_gpio_set_cfgpin(pin, SUNXI_GPD0_LVDS0);
+		sunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LVDS0);
 #endif
 
 	sunxi_lcdc_pll_set(0, mode->pixclock_khz, &clk_div, &clk_double);
@@ -779,8 +779,8 @@ static void sunxi_lcdc_tcon1_mode_set(const struct ctfb_res_modes *mode,
 	       &lcdc->tcon1_timing_sync);
 
 	if (use_portd_hvsync) {
-		sunxi_gpio_set_cfgpin(SUNXI_GPD(26), SUNXI_GPD0_LCD0);
-		sunxi_gpio_set_cfgpin(SUNXI_GPD(27), SUNXI_GPD0_LCD0);
+		sunxi_gpio_set_cfgpin(SUNXI_GPD(26), SUNXI_GPD_LCD0);
+		sunxi_gpio_set_cfgpin(SUNXI_GPD(27), SUNXI_GPD_LCD0);
 
 		val = 0;
 		if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 7+ messages in thread

* [U-Boot] [PATCH 2/3] sunxi: Complete mmc pin mux for each supported platform, configured with Kconfig
  2015-03-22 17:12 [U-Boot] [PATCH 0/3] sunxi: Yones Toptech BD1078 support Paul Kocialkowski
  2015-03-22 17:12 ` [U-Boot] [PATCH 1/3] sunxi: GPIO pin mux hardware-feature-specific function index defines Paul Kocialkowski
@ 2015-03-22 17:12 ` Paul Kocialkowski
  2015-03-22 17:12 ` [U-Boot] [PATCH 3/3] sunxi: Yones Toptech BD1078 support Paul Kocialkowski
                   ` (2 subsequent siblings)
  4 siblings, 0 replies; 7+ messages in thread
From: Paul Kocialkowski @ 2015-03-22 17:12 UTC (permalink / raw)
  To: u-boot

Sunxi platforms have different possible mmc pin mux setups (except for mmc0),
which are different across platforms.

This lets users configure which is used through the CONFIG_MMC*_PINS Kconfig
options. This is especially relevant when a second (in addition to mmc0) port
is used and CONFIG_MMC_SUNXI_SLOT_EXTRA is enabled.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
---
 arch/arm/include/asm/arch-sunxi/gpio.h |  13 +++-
 board/sunxi/Kconfig                    |  19 +++++
 board/sunxi/board.c                    | 131 +++++++++++++++++++++++++++++++--
 drivers/gpio/sunxi_gpio.c              |  14 ++++
 4 files changed, 171 insertions(+), 6 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index a6b15d6..f227044 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -145,26 +145,36 @@ enum sunxi_gpio_number {
 #define SUNXI_GPA_EMAC		2
 #define SUN6I_GPA_GMAC		2
 #define SUN7I_GPA_GMAC		5
+#define SUN6I_GPA_SDC2		5
+#define SUN6I_GPA_SDC3		4
 
 #define SUNXI_GPB_TWI0		2
 #define SUN4I_GPB_UART0		2
 #define SUN5I_GPB_UART0		2
 
 #define SUNXI_GPC_SDC2		3
+#define SUN6I_GPC_SDC3		4
 
+#define SUN8I_GPD_SDC1		3
 #define SUNXI_GPD_LCD0		2
 #define SUNXI_GPD_LVDS0		3
 
+#define SUN5I_GPE_SDC2		3
+
 #define SUNXI_GPF_SDC0		2
 #define SUNXI_GPF_UART0		4
 #define SUN8I_GPF_UART0		3
 
+#define SUN4I_GPG_SDC1		4
 #define SUN5I_GPG_SDC1		2
+#define SUN6I_GPG_SDC1		2
+#define SUN8I_GPG_SDC1		2
 #define SUN5I_GPG_UART1		4
 
+#define SUN4I_GPH_SDC1		5
 #define SUN6I_GPH_UART0		2
 
-#define SUN4I_GPI_SDC3		2
+#define SUNXI_GPI_SDC3		2
 
 #define SUN6I_GPL0_R_P2WI_SCK	3
 #define SUN6I_GPL1_R_P2WI_SDA	3
@@ -189,6 +199,7 @@ int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset);
 int sunxi_gpio_get_cfgpin(u32 pin);
 int sunxi_gpio_set_drv(u32 pin, u32 val);
 int sunxi_gpio_set_pull(u32 pin, u32 val);
+int sunxi_name_to_gpio_bank(const char *name);
 int sunxi_name_to_gpio(const char *name);
 #define name_to_gpio(name) sunxi_name_to_gpio(name)
 
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 5639321..57e7529 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -208,6 +208,25 @@ config MMC3_CD_PIN
 	---help---
 	See MMC0_CD_PIN help text.
 
+config MMC1_PINS
+	string "Pins for mmc1"
+	default ""
+	---help---
+	Set the pins used for mmc1, when applicable. This takes a string in the
+	format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
+
+config MMC2_PINS
+	string "Pins for mmc2"
+	default ""
+	---help---
+	See MMC1_PINS help text.
+
+config MMC3_PINS
+	string "Pins for mmc3"
+	default ""
+	---help---
+	See MMC1_PINS help text.
+
 config MMC_SUNXI_SLOT_EXTRA
 	int "mmc extra slot number"
 	default -1
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 3af3973..01b654e 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -71,10 +71,11 @@ int dram_init(void)
 static void mmc_pinmux_setup(int sdc)
 {
 	unsigned int pin;
+	int pins;
 
 	switch (sdc) {
 	case 0:
-		/* D1-PF0, D0-PF1, CLK-PF2, CMD-PF3, D3-PF4, D4-PF5 */
+		/* SDC0: PF0-PF5 */
 		for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
 			sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
 			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
@@ -83,30 +84,150 @@ static void mmc_pinmux_setup(int sdc)
 		break;
 
 	case 1:
-		/* CMD-PG3, CLK-PG4, D0~D3-PG5-8 */
+		pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
+
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
+		if (pins == SUNXI_GPIO_H) {
+			/* SDC1: PH22-PH-27 */
+			for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
+				sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
+				sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+				sunxi_gpio_set_drv(pin, 2);
+			}
+		} else {
+			/* SDC1: PG0-PG5 */
+			for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
+				sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
+				sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+				sunxi_gpio_set_drv(pin, 2);
+			}
+		}
+#elif defined(CONFIG_MACH_SUN5I)
+		/* SDC1: PG3-PG8 */
 		for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
 			sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
 			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 			sunxi_gpio_set_drv(pin, 2);
 		}
+#elif defined(CONFIG_MACH_SUN6I)
+		/* SDC1: PG0-PG5 */
+		for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
+			sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
+			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+			sunxi_gpio_set_drv(pin, 2);
+		}
+#elif defined(CONFIG_MACH_SUN8I)
+		if (pins == SUNXI_GPIO_D) {
+			/* SDC1: PD2-PD7 */
+			for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
+				sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
+				sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+				sunxi_gpio_set_drv(pin, 2);
+			}
+		} else {
+			/* SDC1: PG0-PG5 */
+			for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
+				sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
+				sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+				sunxi_gpio_set_drv(pin, 2);
+			}
+		}
+#endif
 		break;
 
 	case 2:
-		/* CMD-PC6, CLK-PC7, D0-PC8, D1-PC9, D2-PC10, D3-PC11 */
+		pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
+
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
+		/* SDC2: PC6-PC11 */
 		for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
 			sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
 			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 			sunxi_gpio_set_drv(pin, 2);
 		}
+#elif defined(CONFIG_MACH_SUN5I)
+		if (pins == SUNXI_GPIO_E) {
+			/* SDC2: PE4-PE9 */
+			for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
+				sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
+				sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+				sunxi_gpio_set_drv(pin, 2);
+			}
+		} else {
+			/* SDC2: PC6-PC15 */
+			for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
+				sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
+				sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+				sunxi_gpio_set_drv(pin, 2);
+			}
+		}
+#elif defined(CONFIG_MACH_SUN6I)
+		if (pins == SUNXI_GPIO_A) {
+			/* SDC2: PA9-PA14 */
+			for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
+				sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
+				sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+				sunxi_gpio_set_drv(pin, 2);
+			}
+		} else {
+			/* SDC2: PC6-PC15, PC24 */
+			for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
+				sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
+				sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+				sunxi_gpio_set_drv(pin, 2);
+			}
+
+			sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
+			sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
+			sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
+		}
+#elif defined(CONFIG_MACH_SUN8I)
+		/* SDC2: PC5-PC6, PC8-PC16 */
+		for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
+			sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
+			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+			sunxi_gpio_set_drv(pin, 2);
+		}
+
+		for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
+			sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
+			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+			sunxi_gpio_set_drv(pin, 2);
+		}
+#endif
 		break;
 
 	case 3:
-		/* CMD-PI4, CLK-PI5, D0~D3-PI6~9 : 2 */
+		pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
+
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
+		/* SDC3: PI4-PI9 */
 		for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
-			sunxi_gpio_set_cfgpin(pin, SUN4I_GPI_SDC3);
+			sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
 			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 			sunxi_gpio_set_drv(pin, 2);
 		}
+#elif defined(CONFIG_MACH_SUN6I)
+		if (pins == SUNXI_GPIO_A) {
+			/* SDC3: PA9-PA14 */
+			for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
+				sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
+				sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+				sunxi_gpio_set_drv(pin, 2);
+			}
+		} else {
+			/* SDC3: PC6-PC15, PC24 */
+			for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
+				sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
+				sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+				sunxi_gpio_set_drv(pin, 2);
+			}
+
+			sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
+			sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
+			sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
+		}
+#endif
 		break;
 
 	default:
diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
index c66aa51..532d489 100644
--- a/drivers/gpio/sunxi_gpio.c
+++ b/drivers/gpio/sunxi_gpio.c
@@ -115,6 +115,20 @@ int gpio_set_value(unsigned gpio, int value)
 	return sunxi_gpio_output(gpio, value);
 }
 
+int sunxi_name_to_gpio_bank(const char *name)
+{
+	int group = 0;
+
+	if (*name == 'P' || *name == 'p')
+		name++;
+	if (*name >= 'A') {
+		group = *name - (*name > 'a' ? 'a' : 'A');
+		return group;
+	}
+
+	return -1;
+}
+
 int sunxi_name_to_gpio(const char *name)
 {
 	int group = 0;
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 7+ messages in thread

* [U-Boot] [PATCH 3/3] sunxi: Yones Toptech BD1078 support
  2015-03-22 17:12 [U-Boot] [PATCH 0/3] sunxi: Yones Toptech BD1078 support Paul Kocialkowski
  2015-03-22 17:12 ` [U-Boot] [PATCH 1/3] sunxi: GPIO pin mux hardware-feature-specific function index defines Paul Kocialkowski
  2015-03-22 17:12 ` [U-Boot] [PATCH 2/3] sunxi: Complete mmc pin mux for each supported platform, configured with Kconfig Paul Kocialkowski
@ 2015-03-22 17:12 ` Paul Kocialkowski
  2015-03-23 16:24 ` [U-Boot] [PATCH 0/3] " Hans de Goede
  2015-03-23 16:26 ` Hans de Goede
  4 siblings, 0 replies; 7+ messages in thread
From: Paul Kocialkowski @ 2015-03-22 17:12 UTC (permalink / raw)
  To: u-boot

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
---
 board/sunxi/MAINTAINERS                |  5 +++++
 configs/Yones_Toptech_BD1078_defconfig | 21 +++++++++++++++++++++
 2 files changed, 26 insertions(+)
 create mode 100644 configs/Yones_Toptech_BD1078_defconfig

diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index e486458..28c7144 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -148,3 +148,8 @@ WEXLER-TAB7200 BOARD
 M:	Aleksei Mamlin <mamlinav@gmail.com>
 S:	Maintained
 F:	configs/Wexler_TAB7200_defconfig
+
+YONES TOPTECH BD1078 BOARD
+M:	Paul Kocialkowski <contact@paulk.fr>
+S:	Maintained
+F:	configs/Yones_Toptech_BD1078_defconfig
diff --git a/configs/Yones_Toptech_BD1078_defconfig b/configs/Yones_Toptech_BD1078_defconfig
new file mode 100644
index 0000000..cddbbb5
--- /dev/null
+++ b/configs/Yones_Toptech_BD1078_defconfig
@@ -0,0 +1,21 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER"
+CONFIG_FDTFILE="sun7i-a20-yones-toptech-bd1078.dtb"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=1
+CONFIG_MMC1_PINS="PH"
+CONFIG_USB_MUSB_SUNXI=y
+CONFIG_USB0_VBUS_PIN="PB9"
+CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
+CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:24,pclk_khz:63000,le:32,ri:287,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_DCLK_PHASE=0
+CONFIG_VIDEO_LCD_PANEL_LVDS=y
+CONFIG_VIDEO_LCD_POWER="PH8"
+CONFIG_VIDEO_LCD_BL_EN="PH7"
+CONFIG_VIDEO_LCD_BL_PWM="PB2"
+CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW=n
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=408
+CONFIG_DRAM_ZQ=127
+CONFIG_DRAM_EMR1=4
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 7+ messages in thread

* [U-Boot] [PATCH 0/3] sunxi: Yones Toptech BD1078 support
  2015-03-22 17:12 [U-Boot] [PATCH 0/3] sunxi: Yones Toptech BD1078 support Paul Kocialkowski
                   ` (2 preceding siblings ...)
  2015-03-22 17:12 ` [U-Boot] [PATCH 3/3] sunxi: Yones Toptech BD1078 support Paul Kocialkowski
@ 2015-03-23 16:24 ` Hans de Goede
  2015-03-23 16:26 ` Hans de Goede
  4 siblings, 0 replies; 7+ messages in thread
From: Hans de Goede @ 2015-03-23 16:24 UTC (permalink / raw)
  To: u-boot

Hi,

Thanks.

The entire set has been queued up in u-boot-sunxi/next for upstream merging.

Regards,

Hans


On 22-03-15 18:12, Paul Kocialkowski wrote:
> This series goes on top of my previous series that concludes with Ainol AW1
> support.
>
> Also, if you're interested by the idea of using sunxi_name_to_gpio_bank, this
> could be extended for UART as well, where *many* different pin mux setups are
> possible. We are just lucky that hardware designers usually use the ports that
> U-Boot selects, but there is no fundamental reason for that.
>

^ permalink raw reply	[flat|nested] 7+ messages in thread

* [U-Boot] [PATCH 0/3] sunxi: Yones Toptech BD1078 support
  2015-03-22 17:12 [U-Boot] [PATCH 0/3] sunxi: Yones Toptech BD1078 support Paul Kocialkowski
                   ` (3 preceding siblings ...)
  2015-03-23 16:24 ` [U-Boot] [PATCH 0/3] " Hans de Goede
@ 2015-03-23 16:26 ` Hans de Goede
  2015-03-23 16:28   ` Paul Kocialkowski
  4 siblings, 1 reply; 7+ messages in thread
From: Hans de Goede @ 2015-03-23 16:26 UTC (permalink / raw)
  To: u-boot

Hi,

p.s.


On 22-03-15 18:12, Paul Kocialkowski wrote:
> This series goes on top of my previous series that concludes with Ainol AW1
> support.
>
> Also, if you're interested by the idea of using sunxi_name_to_gpio_bank, this
> could be extended for UART as well, where *many* different pin mux setups are
> possible. We are just lucky that hardware designers usually use the ports that
> U-Boot selects, but there is no fundamental reason for that.

I'm not really interested in making the #ifdeffery for the uart setup even
more complicated, eventually we should get all this info, including all the
pinmux stuff from a dtb (shared with the kernel) appended to the u-boot binary,
and then this will use standard devicetree pinmux stuff, until we get there
I would like to keep this as simple as possible.

Regards,

Hans

^ permalink raw reply	[flat|nested] 7+ messages in thread

* [U-Boot] [PATCH 0/3] sunxi: Yones Toptech BD1078 support
  2015-03-23 16:26 ` Hans de Goede
@ 2015-03-23 16:28   ` Paul Kocialkowski
  0 siblings, 0 replies; 7+ messages in thread
From: Paul Kocialkowski @ 2015-03-23 16:28 UTC (permalink / raw)
  To: u-boot

Le lundi 23 mars 2015 ? 17:26 +0100, Hans de Goede a ?crit :
> Hi,
> 
> p.s.
> 
> 
> On 22-03-15 18:12, Paul Kocialkowski wrote:
> > This series goes on top of my previous series that concludes with Ainol AW1
> > support.
> >
> > Also, if you're interested by the idea of using sunxi_name_to_gpio_bank, this
> > could be extended for UART as well, where *many* different pin mux setups are
> > possible. We are just lucky that hardware designers usually use the ports that
> > U-Boot selects, but there is no fundamental reason for that.
> 
> I'm not really interested in making the #ifdeffery for the uart setup even
> more complicated, eventually we should get all this info, including all the
> pinmux stuff from a dtb (shared with the kernel) appended to the u-boot binary,
> and then this will use standard devicetree pinmux stuff, until we get there
> I would like to keep this as simple as possible.

Understood. There was a real need for mmc as the previous setups were
just wrong for platforms != (sun4i || sun7i), but in the case of UART,
it just remains minimalistic, which is fine.

-- 
Paul Kocialkowski, Replicant developer

Replicant is a fully free Android distribution running on several
devices, a free software mobile operating system putting the emphasis on
freedom and privacy/security.

Website: http://www.replicant.us/
Blog: http://blog.replicant.us/
Wiki/tracker/forums: http://redmine.replicant.us/

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^ permalink raw reply	[flat|nested] 7+ messages in thread

end of thread, other threads:[~2015-03-23 16:28 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2015-03-22 17:12 [U-Boot] [PATCH 0/3] sunxi: Yones Toptech BD1078 support Paul Kocialkowski
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2015-03-22 17:12 ` [U-Boot] [PATCH 2/3] sunxi: Complete mmc pin mux for each supported platform, configured with Kconfig Paul Kocialkowski
2015-03-22 17:12 ` [U-Boot] [PATCH 3/3] sunxi: Yones Toptech BD1078 support Paul Kocialkowski
2015-03-23 16:24 ` [U-Boot] [PATCH 0/3] " Hans de Goede
2015-03-23 16:26 ` Hans de Goede
2015-03-23 16:28   ` Paul Kocialkowski

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