From mboxrd@z Thu Jan 1 00:00:00 1970 From: York Sun Date: Tue, 24 Mar 2015 09:46:14 -0700 Subject: [U-Boot] [PATCH v5 24/28] armv8/ls2085aqds: NAND boot support In-Reply-To: References: <1426904912-29186-1-git-send-email-yorksun@freescale.com> <1426904912-29186-25-git-send-email-yorksun@freescale.com> <1427160845.22867.43.camel@freescale.com> <55118683.6060608@freescale.com> Message-ID: <551194D6.9040101@freescale.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 03/24/2015 09:34 AM, Kushwaha Prabhakar-B32579 wrote: > >> -----Original Message----- >> From: Sun York-R58495 >> Sent: Tuesday, March 24, 2015 9:15 PM >> To: Wood Scott-B07421 >> Cc: u-boot at lists.denx.de; Kushwaha Prabhakar-B32579 >> Subject: Re: [PATCH v5 24/28] armv8/ls2085aqds: NAND boot support >> >> >> >> On 03/23/2015 06:34 PM, Scott Wood wrote: >>> On Fri, 2015-03-20 at 19:28 -0700, York Sun wrote: >>>> +Generage NAND image >>>> +------------------- >>>> +To form the NAND image, build u-boot with LS2085AQDS_NAND_defconfig. >>>> +Append u-boot-with-spl.bin after RCW image. The RCW image should >>>> +have these PBI commands >>>> + >>>> +1) CCSR 4-byte write to 0x00e00404, data=0x00000000 >>>> +2) CCSR 4-byte write to 0x00e00400, data=0x1800a000 >>>> +3) Block Copy: SRC=0x0104, SRC_ADDR=0x000000c0, >>>> +DEST_ADDR=0x1800a000, >>>> +BLOCK_SIZE=0x00014000 >>> >>> The RCW source should probably be 0x107, not 0x104. Bit 0x002 >>> requests first/last bad block markers rather than first/second, and >>> bit 0x001 enables ECC. Also, this documentation is LS2085A-specific >>> (most of it will probably apply to all chips with this chassis), not >>> RDB or QDS specific, with the exception of the RCW source ID which >>> depends on the specific NAND chip. It would be better to put it in >>> one place rather than duplicate it, with a table of RCW source IDs for each >> board. >>> >>> Also, you have RDB as having SRC=0x104, but that (as well as 0x107) is >>> for a 2K-page NAND chip. RDB has a 4K-page NAND, so I think you want >>> RCW source to be 0x111. >>> >> > for RDB. I think RCW source should be 0x119. > bad block at first/last page(ONFI requirement) and 4bit ECC > I think 0x119 is correct. It is the same value I read back from rcw_src. I just verified it boots OK. I have been using 0x104 as the source id incorrectly but it also boots. York