From: Iain Paton <ipaton0@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 1/3] sunxi: sun4i: add missing 912MHz clock divisors
Date: Fri, 27 Mar 2015 00:10:59 +0000 [thread overview]
Message-ID: <5514A013.7040300@gmail.com> (raw)
clock divisors table was missing an entry for 912MHz. The same table is
used for sun7i where the default boot clock is 912MHz, resulting in A20
boards being overclocked to 960MHz
Signed-off-by: Iain Paton <ipaton0@gmail.com>
---
arch/arm/cpu/armv7/sunxi/clock_sun4i.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
index 49f4032..c720e96 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
@@ -102,6 +102,7 @@ static struct {
/* This array must be ordered by frequency. */
{ PLL1_CFG(16, 0, 0, 0), 384000000 },
{ PLL1_CFG(16, 1, 0, 0), 768000000 },
+ { PLL1_CFG(19, 1, 0, 0), 912000000 },
{ PLL1_CFG(20, 1, 0, 0), 960000000 },
{ PLL1_CFG(21, 1, 0, 0), 1008000000},
{ PLL1_CFG(22, 1, 0, 0), 1056000000},
--
2.1.3
next reply other threads:[~2015-03-27 0:10 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-27 0:10 Iain Paton [this message]
2015-03-27 14:04 ` [U-Boot] [PATCH 1/3] sunxi: sun4i: add missing 912MHz clock divisors Ian Campbell
2015-03-28 10:24 ` Iain Paton
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