From: Iain Paton <ipaton0@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 1/3] sunxi: sun4i: add missing 912MHz clock divisors
Date: Sat, 28 Mar 2015 10:24:49 +0000 [thread overview]
Message-ID: <55168171.2000200@gmail.com> (raw)
In-Reply-To: <1427465093.13935.151.camel@hellion.org.uk>
On 27/03/15 14:04, Ian Campbell wrote:
> On Fri, 2015-03-27 at 00:10 +0000, Iain Paton wrote:
>> clock divisors table was missing an entry for 912MHz. The same table is
>> used for sun7i where the default boot clock is 912MHz, resulting in A20
>> boards being overclocked to 960MHz
>
> Apart from the missing entry, should it not be the case that we pick the
> highest frequency <= than the requested frequency, rather than the next
> available (potentially higher) frequency?
>
> IOW I'd expect things to be underclocked at 768MHz without this change,
> which would mean that clock_set_pll1 is buggy.
Perhaps, however the selection algorithm is so trivial that I have
difficulty beleiving that picking next highest was anything other than
deliberate and the intended outcome.
I'll send a revised version that changes it to next lowest.
Rgds,
Iain
prev parent reply other threads:[~2015-03-28 10:24 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-27 0:10 [U-Boot] [PATCH 1/3] sunxi: sun4i: add missing 912MHz clock divisors Iain Paton
2015-03-27 14:04 ` Ian Campbell
2015-03-28 10:24 ` Iain Paton [this message]
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