From mboxrd@z Thu Jan 1 00:00:00 1970 From: Iain Paton Date: Sat, 28 Mar 2015 10:24:49 +0000 Subject: [U-Boot] [PATCH 1/3] sunxi: sun4i: add missing 912MHz clock divisors In-Reply-To: <1427465093.13935.151.camel@hellion.org.uk> References: <5514A013.7040300@gmail.com> <1427465093.13935.151.camel@hellion.org.uk> Message-ID: <55168171.2000200@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 27/03/15 14:04, Ian Campbell wrote: > On Fri, 2015-03-27 at 00:10 +0000, Iain Paton wrote: >> clock divisors table was missing an entry for 912MHz. The same table is >> used for sun7i where the default boot clock is 912MHz, resulting in A20 >> boards being overclocked to 960MHz > > Apart from the missing entry, should it not be the case that we pick the > highest frequency <= than the requested frequency, rather than the next > available (potentially higher) frequency? > > IOW I'd expect things to be underclocked at 768MHz without this change, > which would mean that clock_set_pll1 is buggy. Perhaps, however the selection algorithm is so trivial that I have difficulty beleiving that picking next highest was anything other than deliberate and the intended outcome. I'll send a revised version that changes it to next lowest. Rgds, Iain