[U-Boot] [PATCH v7 00/17] Add PSCI support for Jetson TK1/Tegra124 + CNTFRQ fix

[U-Boot] [PATCH v7 00/17] Add PSCI support for Jetson TK1/Tegra124 + CNTFRQ fix

[Jan Kiszka]

Changes in v7:
 - rebased over master
 - fixed issue that prevented secure boot with all cores
   => replace ap_pm_init with psci_board_init hook
 - enable CONFIG_ARMV7_BOOT_SEC_DEFAULT for tegra to avoid problems with
   default config of current Linux
 - add cleanup patch for CONFIG_ARMV7_NONSEC/VIRT/PSCI

Note that I've removed reviewed and tested tags from modified patches.

Jan

CC: Andre Przywara <andre.przywara@linaro.org>
CC: Ian Campbell <ijc@hellion.org.uk>
CC: Marc Zyngier <marc.zyngier@arm.com>
CC: Steve Rae <srae@broadcom.com>
CC: Tang Yuantian <Yuantian.Tang@freescale.com>
CC: Thierry Reding <treding@nvidia.com>
CC: York Sun <yorksun@freescale.com>

Ian Campbell (3):
  tegra124: Add more registers to struct mc_ctlr
  tegra124: Reserve secure RAM using MC_SECURITY_CFG{0, 1}_0
  jetson-tk1: Add PSCI configuration options and reserve secure code

Jan Kiszka (13):
  ARM: Clean up CONFIG_ARMV7_NONSEC/VIRT/PSCI conditions
  sun7i: Remove duplicate call to psci_arch_init
  ARM: Factor out common psci_get_cpu_id
  ARM: Factor out reusable psci_cpu_off_common
  ARM: Factor out reusable psci_cpu_entry
  ARM: Factor out reusable psci_get_cpu_stack_top
  ARM: Put target PC for PSCI CPU_ON on per-CPU stack
  virt-dt: Allow reservation of secure region when in a RAM carveout
  tegra: Make tegra_powergate_power_on public
  ARM: Add board-specific initialization hook for PSCI
  tegra124: Add PSCI support for Tegra124
  tegra: Set CNTFRQ for secondary CPUs
  tegra: Boot in non-secure mode by default

Thierry Reding (1):
  ARM: tegra: Enable SMMU when going non-secure

 arch/arm/cpu/armv7/Kconfig                  |   2 +-
 arch/arm/cpu/armv7/Makefile                 |   2 +-
 arch/arm/cpu/armv7/ls102xa/cpu.c            |   2 +-
 arch/arm/cpu/armv7/psci.S                   | 121 ++++++++++++++++++++++++++++
 arch/arm/cpu/armv7/sunxi/psci.S             | 112 ++++---------------------
 arch/arm/cpu/armv7/virt-dt.c                |  31 ++++++-
 arch/arm/cpu/armv7/virt-v7.c                |  11 +++
 arch/arm/cpu/u-boot.lds                     |   2 +-
 arch/arm/include/asm/arch-tegra/powergate.h |   1 +
 arch/arm/include/asm/arch-tegra124/flow.h   |   6 ++
 arch/arm/include/asm/arch-tegra124/mc.h     |  37 ++++++++-
 arch/arm/include/asm/armv7.h                |   5 +-
 arch/arm/include/asm/psci.h                 |   1 +
 arch/arm/include/asm/system.h               |   1 +
 arch/arm/lib/bootm-fdt.c                    |   8 +-
 arch/arm/lib/bootm.c                        |   6 +-
 arch/arm/mach-tegra/Makefile                |   4 +
 arch/arm/mach-tegra/ap.c                    |  55 +++++++++++++
 arch/arm/mach-tegra/powergate.c             |   2 +-
 arch/arm/mach-tegra/psci.S                  | 114 ++++++++++++++++++++++++++
 arch/arm/mach-tegra/tegra124/Kconfig        |   2 +
 arch/arm/mach-tegra/tegra124/Makefile       |   4 +
 arch/arm/mach-tegra/tegra124/psci.c         |  59 ++++++++++++++
 board/armltd/vexpress/vexpress_common.c     |   2 +-
 board/broadcom/bcm_ep/board.c               |   2 +-
 board/freescale/common/arm_sleep.c          |   2 +-
 include/configs/jetson-tk1.h                |   5 ++
 27 files changed, 487 insertions(+), 112 deletions(-)
 create mode 100644 arch/arm/mach-tegra/psci.S
 create mode 100644 arch/arm/mach-tegra/tegra124/psci.c

-- 
2.1.4

[U-Boot] [PATCH v7 01/17] ARM: Clean up CONFIG_ARMV7_NONSEC/VIRT/PSCI conditions

[Jan Kiszka]

CONFIG_ARMV7_VIRT depends on CONFIG_ARMV7_NONSEC, thus doesn't need to
be taken into account additionally. CONFIG_ARMV7_PSCI is only set on
boards that support CONFIG_ARMV7_NONSEC, and it only works on those.

CC: Tang Yuantian <Yuantian.Tang@freescale.com>
CC: York Sun <yorksun@freescale.com>
CC: Steve Rae <srae@broadcom.com>
CC: Andre Przywara <andre.przywara@linaro.org>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
---
 arch/arm/cpu/armv7/Makefile             | 2 +-
 arch/arm/cpu/armv7/ls102xa/cpu.c        | 2 +-
 arch/arm/cpu/armv7/virt-dt.c            | 2 +-
 arch/arm/cpu/u-boot.lds                 | 2 +-
 arch/arm/include/asm/armv7.h            | 4 ++--
 arch/arm/lib/bootm-fdt.c                | 2 +-
 arch/arm/lib/bootm.c                    | 6 +++---
 board/armltd/vexpress/vexpress_common.c | 2 +-
 board/broadcom/bcm_ep/board.c           | 2 +-
 board/freescale/common/arm_sleep.c      | 2 +-
 10 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 21fc03b..fbd0bf3 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -18,7 +18,7 @@ obj-y	+= lowlevel_init.o
 endif
 endif
 
-ifneq ($(CONFIG_ARMV7_NONSEC)$(CONFIG_ARMV7_VIRT),)
+ifneq ($(CONFIG_ARMV7_NONSEC),)
 obj-y	+= nonsec_virt.o
 obj-y	+= virt-v7.o
 obj-y	+= virt-dt.o
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index 1a640bb..75f0d8c 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -329,7 +329,7 @@ int arch_cpu_init(void)
 	return 0;
 }
 
-#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+#ifdef CONFIG_ARMV7_NONSEC
 /* Set the address at which the secondary core starts from.*/
 void smp_set_core_boot_addr(unsigned long addr, int corenr)
 {
diff --git a/arch/arm/cpu/armv7/virt-dt.c b/arch/arm/cpu/armv7/virt-dt.c
index 9408e33..caaaaab 100644
--- a/arch/arm/cpu/armv7/virt-dt.c
+++ b/arch/arm/cpu/armv7/virt-dt.c
@@ -90,7 +90,7 @@ static int fdt_psci(void *fdt)
 
 int psci_update_dt(void *fdt)
 {
-#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+#ifdef CONFIG_ARMV7_NONSEC
 	if (!armv7_boot_nonsec())
 		return 0;
 #endif
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index 7336162..03cd9f6 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -25,7 +25,7 @@ SECTIONS
 		*(.text*)
 	}
 
-#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) || defined(CONFIG_ARMV7_PSCI)
+#ifdef CONFIG_ARMV7_NONSEC
 
 #ifndef CONFIG_ARMV7_SECURE_BASE
 #define CONFIG_ARMV7_SECURE_BASE
diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
index 58d8b16..2bb1253 100644
--- a/arch/arm/include/asm/armv7.h
+++ b/arch/arm/include/asm/armv7.h
@@ -121,7 +121,7 @@ void v7_outer_cache_inval_all(void);
 void v7_outer_cache_flush_range(u32 start, u32 end);
 void v7_outer_cache_inval_range(u32 start, u32 end);
 
-#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+#ifdef CONFIG_ARMV7_NONSEC
 
 int armv7_init_nonsec(void);
 bool armv7_boot_nonsec(void);
@@ -135,7 +135,7 @@ void _smp_pen(void);
 extern char __secure_start[];
 extern char __secure_end[];
 
-#endif /* CONFIG_ARMV7_NONSEC || CONFIG_ARMV7_VIRT */
+#endif /* CONFIG_ARMV7_NONSEC */
 
 void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
 				 u32 cpu_rev_comb, u32 cpu_variant,
diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c
index 665a3bc..49ba691 100644
--- a/arch/arm/lib/bootm-fdt.c
+++ b/arch/arm/lib/bootm-fdt.c
@@ -34,7 +34,7 @@ int arch_fixup_fdt(void *blob)
 	}
 
 	ret = fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
-#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+#ifdef CONFIG_ARMV7_NONSEC
 	if (ret)
 		return ret;
 
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index b1bff8c..ee56d74 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -26,7 +26,7 @@
 #include <bootm.h>
 #include <vxworks.h>
 
-#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+#ifdef CONFIG_ARMV7_NONSEC
 #include <asm/armv7.h>
 #endif
 
@@ -238,7 +238,7 @@ static void boot_prep_linux(bootm_headers_t *images)
 	}
 }
 
-#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+#ifdef CONFIG_ARMV7_NONSEC
 bool armv7_boot_nonsec(void)
 {
 	char *s = getenv("bootm_boot_mode");
@@ -305,7 +305,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
 		r2 = gd->bd->bi_boot_params;
 
 	if (!fake) {
-#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+#ifdef CONFIG_ARMV7_NONSEC
 		if (armv7_boot_nonsec()) {
 			armv7_init_nonsec();
 			secure_ram_addr(_do_nonsec_entry)(kernel_entry,
diff --git a/board/armltd/vexpress/vexpress_common.c b/board/armltd/vexpress/vexpress_common.c
index cb2de2f..d3b3b31 100644
--- a/board/armltd/vexpress/vexpress_common.c
+++ b/board/armltd/vexpress/vexpress_common.c
@@ -181,7 +181,7 @@ ulong get_board_rev(void){
 	return readl((u32 *)SYS_ID);
 }
 
-#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+#ifdef CONFIG_ARMV7_NONSEC
 /* Setting the address at which secondary cores start from.
  * Versatile Express uses one address for all cores, so ignore corenr
  */
diff --git a/board/broadcom/bcm_ep/board.c b/board/broadcom/bcm_ep/board.c
index 6a70a2e..eaad0b3 100644
--- a/board/broadcom/bcm_ep/board.c
+++ b/board/broadcom/bcm_ep/board.c
@@ -54,7 +54,7 @@ int board_early_init_f(void)
 	return status;
 }
 
-#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+#ifdef CONFIG_ARMV7_NONSEC
 void smp_set_core_boot_addr(unsigned long addr, int corenr)
 {
 }
diff --git a/board/freescale/common/arm_sleep.c b/board/freescale/common/arm_sleep.c
index 8edf878..30d9c7b 100644
--- a/board/freescale/common/arm_sleep.c
+++ b/board/freescale/common/arm_sleep.c
@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#if !defined(CONFIG_ARMV7_NONSEC) || !defined(CONFIG_ARMV7_VIRT)
+#ifndef CONFIG_ARMV7_NONSEC
 #error " Deep sleep needs non-secure mode support. "
 #else
 #include <asm/secure.h>
-- 
2.1.4

[U-Boot] [PATCH v7 01/17] ARM: Clean up CONFIG_ARMV7_NONSEC/VIRT/PSCI conditions

[Huan Wang]

Hi, Jan,

> 
> CONFIG_ARMV7_VIRT depends on CONFIG_ARMV7_NONSEC, thus doesn't need to
> be taken into account additionally. CONFIG_ARMV7_PSCI is only set on
> boards that support CONFIG_ARMV7_NONSEC, and it only works on those.
> 
> CC: Tang Yuantian <Yuantian.Tang@freescale.com>
> CC: York Sun <yorksun@freescale.com>
> CC: Steve Rae <srae@broadcom.com>
> CC: Andre Przywara <andre.przywara@linaro.org>
> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
> 

I confirmed this on LS1021AQDS/TWR boards.

Tested-by: Alison Wang <alison.wang@freescale.com>


Best Regards,
Alison Wang

[U-Boot] [PATCH v7 01/17] ARM: Clean up CONFIG_ARMV7_NONSEC/VIRT/PSCI conditions

[Andre Przywara]

On Tue, 21 Apr 2015 07:18:24 +0200
Jan Kiszka <jan.kiszka@siemens.com> wrote:

Hi Jan,

> CONFIG_ARMV7_VIRT depends on CONFIG_ARMV7_NONSEC,

Is this Kconfig rule always enforced these days? Or can one get away
without it by using stuff from include/configs/*.h?

> thus doesn't need to
> be taken into account additionally. CONFIG_ARMV7_PSCI is only set on
> boards that support CONFIG_ARMV7_NONSEC, and it only works on those.

Shouldn't this be also modelled in Kconfig then?

...

> CC: Tang Yuantian <Yuantian.Tang@freescale.com>
> CC: York Sun <yorksun@freescale.com>
> CC: Steve Rae <srae@broadcom.com>
> CC: Andre Przywara <andre.przywara@linaro.org>
> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
> ---
>  arch/arm/cpu/armv7/Makefile             | 2 +-
>  arch/arm/cpu/armv7/ls102xa/cpu.c        | 2 +-
>  arch/arm/cpu/armv7/virt-dt.c            | 2 +-
>  arch/arm/cpu/u-boot.lds                 | 2 +-
>  arch/arm/include/asm/armv7.h            | 4 ++--
>  arch/arm/lib/bootm-fdt.c                | 2 +-
>  arch/arm/lib/bootm.c                    | 6 +++---
>  board/armltd/vexpress/vexpress_common.c | 2 +-
>  board/broadcom/bcm_ep/board.c           | 2 +-
>  board/freescale/common/arm_sleep.c      | 2 +-
>  10 files changed, 13 insertions(+), 13 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
> index 21fc03b..fbd0bf3 100644
> --- a/arch/arm/cpu/armv7/Makefile
> +++ b/arch/arm/cpu/armv7/Makefile
> @@ -18,7 +18,7 @@ obj-y	+= lowlevel_init.o
>  endif
>  endif
>  
> -ifneq ($(CONFIG_ARMV7_NONSEC)$(CONFIG_ARMV7_VIRT),)
> +ifneq ($(CONFIG_ARMV7_NONSEC),)
>  obj-y	+= nonsec_virt.o
>  obj-y	+= virt-v7.o
>  obj-y	+= virt-dt.o
> diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
> index 1a640bb..75f0d8c 100644
> --- a/arch/arm/cpu/armv7/ls102xa/cpu.c
> +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
> @@ -329,7 +329,7 @@ int arch_cpu_init(void)
>  	return 0;
>  }
>  
> -#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
> +#ifdef CONFIG_ARMV7_NONSEC
>  /* Set the address at which the secondary core starts from.*/
>  void smp_set_core_boot_addr(unsigned long addr, int corenr)
>  {
> diff --git a/arch/arm/cpu/armv7/virt-dt.c b/arch/arm/cpu/armv7/virt-dt.c
> index 9408e33..caaaaab 100644
> --- a/arch/arm/cpu/armv7/virt-dt.c
> +++ b/arch/arm/cpu/armv7/virt-dt.c
> @@ -90,7 +90,7 @@ static int fdt_psci(void *fdt)
>  
>  int psci_update_dt(void *fdt)
>  {
> -#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
> +#ifdef CONFIG_ARMV7_NONSEC

This is redundant now, isn't it? We compile this file only if
CONFIG_ARMV7_NONSEC is defined (see above).

The rest of the patch looks OK to me.

Cheers,
Andre.

>  	if (!armv7_boot_nonsec())
>  		return 0;
>  #endif
> diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
> index 7336162..03cd9f6 100644
> --- a/arch/arm/cpu/u-boot.lds
> +++ b/arch/arm/cpu/u-boot.lds
> @@ -25,7 +25,7 @@ SECTIONS
>  		*(.text*)
>  	}
>  
> -#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) || defined(CONFIG_ARMV7_PSCI)
> +#ifdef CONFIG_ARMV7_NONSEC
>  
>  #ifndef CONFIG_ARMV7_SECURE_BASE
>  #define CONFIG_ARMV7_SECURE_BASE
> diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
> index 58d8b16..2bb1253 100644
> --- a/arch/arm/include/asm/armv7.h
> +++ b/arch/arm/include/asm/armv7.h
> @@ -121,7 +121,7 @@ void v7_outer_cache_inval_all(void);
>  void v7_outer_cache_flush_range(u32 start, u32 end);
>  void v7_outer_cache_inval_range(u32 start, u32 end);
>  
> -#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
> +#ifdef CONFIG_ARMV7_NONSEC
>  
>  int armv7_init_nonsec(void);
>  bool armv7_boot_nonsec(void);
> @@ -135,7 +135,7 @@ void _smp_pen(void);
>  extern char __secure_start[];
>  extern char __secure_end[];
>  
> -#endif /* CONFIG_ARMV7_NONSEC || CONFIG_ARMV7_VIRT */
> +#endif /* CONFIG_ARMV7_NONSEC */
>  
>  void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
>  				 u32 cpu_rev_comb, u32 cpu_variant,
> diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c
> index 665a3bc..49ba691 100644
> --- a/arch/arm/lib/bootm-fdt.c
> +++ b/arch/arm/lib/bootm-fdt.c
> @@ -34,7 +34,7 @@ int arch_fixup_fdt(void *blob)
>  	}
>  
>  	ret = fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
> -#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
> +#ifdef CONFIG_ARMV7_NONSEC
>  	if (ret)
>  		return ret;
>  
> diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
> index b1bff8c..ee56d74 100644
> --- a/arch/arm/lib/bootm.c
> +++ b/arch/arm/lib/bootm.c
> @@ -26,7 +26,7 @@
>  #include <bootm.h>
>  #include <vxworks.h>
>  
> -#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
> +#ifdef CONFIG_ARMV7_NONSEC
>  #include <asm/armv7.h>
>  #endif
>  
> @@ -238,7 +238,7 @@ static void boot_prep_linux(bootm_headers_t *images)
>  	}
>  }
>  
> -#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
> +#ifdef CONFIG_ARMV7_NONSEC
>  bool armv7_boot_nonsec(void)
>  {
>  	char *s = getenv("bootm_boot_mode");
> @@ -305,7 +305,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
>  		r2 = gd->bd->bi_boot_params;
>  
>  	if (!fake) {
> -#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
> +#ifdef CONFIG_ARMV7_NONSEC
>  		if (armv7_boot_nonsec()) {
>  			armv7_init_nonsec();
>  			secure_ram_addr(_do_nonsec_entry)(kernel_entry,
> diff --git a/board/armltd/vexpress/vexpress_common.c b/board/armltd/vexpress/vexpress_common.c
> index cb2de2f..d3b3b31 100644
> --- a/board/armltd/vexpress/vexpress_common.c
> +++ b/board/armltd/vexpress/vexpress_common.c
> @@ -181,7 +181,7 @@ ulong get_board_rev(void){
>  	return readl((u32 *)SYS_ID);
>  }
>  
> -#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
> +#ifdef CONFIG_ARMV7_NONSEC
>  /* Setting the address at which secondary cores start from.
>   * Versatile Express uses one address for all cores, so ignore corenr
>   */
> diff --git a/board/broadcom/bcm_ep/board.c b/board/broadcom/bcm_ep/board.c
> index 6a70a2e..eaad0b3 100644
> --- a/board/broadcom/bcm_ep/board.c
> +++ b/board/broadcom/bcm_ep/board.c
> @@ -54,7 +54,7 @@ int board_early_init_f(void)
>  	return status;
>  }
>  
> -#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
> +#ifdef CONFIG_ARMV7_NONSEC
>  void smp_set_core_boot_addr(unsigned long addr, int corenr)
>  {
>  }
> diff --git a/board/freescale/common/arm_sleep.c b/board/freescale/common/arm_sleep.c
> index 8edf878..30d9c7b 100644
> --- a/board/freescale/common/arm_sleep.c
> +++ b/board/freescale/common/arm_sleep.c
> @@ -6,7 +6,7 @@
>  
>  #include <common.h>
>  #include <asm/io.h>
> -#if !defined(CONFIG_ARMV7_NONSEC) || !defined(CONFIG_ARMV7_VIRT)
> +#ifndef CONFIG_ARMV7_NONSEC
>  #error " Deep sleep needs non-secure mode support. "
>  #else
>  #include <asm/secure.h>

[U-Boot] [PATCH v7 01/17] ARM: Clean up CONFIG_ARMV7_NONSEC/VIRT/PSCI conditions

[Jan Kiszka]

On 2015-04-22 16:03, Andre Przywara wrote:
> On Tue, 21 Apr 2015 07:18:24 +0200
> Jan Kiszka <jan.kiszka@siemens.com> wrote:
> 
> Hi Jan,
> 
>> CONFIG_ARMV7_VIRT depends on CONFIG_ARMV7_NONSEC,
> 
> Is this Kconfig rule always enforced these days? Or can one get away
> without it by using stuff from include/configs/*.h?

I bet you can mess up a lot that way as those configs are pulled in
during build, not during configure. But I don't think we want to
replicate Kconfig rules into config header sanity checks.

Fact is that only Freescale's ls1021aqds.h and ls1021atwr.h still set
those switches in headers, but then both hardwired to "y" - do you know
why, Alison?

> 
>> thus doesn't need to
>> be taken into account additionally. CONFIG_ARMV7_PSCI is only set on
>> boards that support CONFIG_ARMV7_NONSEC, and it only works on those.
> 
> Shouldn't this be also modelled in Kconfig then?
> 

Likely, but that should be a separate patch.

> ...
> 
>> CC: Tang Yuantian <Yuantian.Tang@freescale.com>
>> CC: York Sun <yorksun@freescale.com>
>> CC: Steve Rae <srae@broadcom.com>
>> CC: Andre Przywara <andre.przywara@linaro.org>
>> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
>> ---
>>  arch/arm/cpu/armv7/Makefile             | 2 +-
>>  arch/arm/cpu/armv7/ls102xa/cpu.c        | 2 +-
>>  arch/arm/cpu/armv7/virt-dt.c            | 2 +-
>>  arch/arm/cpu/u-boot.lds                 | 2 +-
>>  arch/arm/include/asm/armv7.h            | 4 ++--
>>  arch/arm/lib/bootm-fdt.c                | 2 +-
>>  arch/arm/lib/bootm.c                    | 6 +++---
>>  board/armltd/vexpress/vexpress_common.c | 2 +-
>>  board/broadcom/bcm_ep/board.c           | 2 +-
>>  board/freescale/common/arm_sleep.c      | 2 +-
>>  10 files changed, 13 insertions(+), 13 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
>> index 21fc03b..fbd0bf3 100644
>> --- a/arch/arm/cpu/armv7/Makefile
>> +++ b/arch/arm/cpu/armv7/Makefile
>> @@ -18,7 +18,7 @@ obj-y	+= lowlevel_init.o
>>  endif
>>  endif
>>  
>> -ifneq ($(CONFIG_ARMV7_NONSEC)$(CONFIG_ARMV7_VIRT),)
>> +ifneq ($(CONFIG_ARMV7_NONSEC),)
>>  obj-y	+= nonsec_virt.o
>>  obj-y	+= virt-v7.o
>>  obj-y	+= virt-dt.o
>> diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
>> index 1a640bb..75f0d8c 100644
>> --- a/arch/arm/cpu/armv7/ls102xa/cpu.c
>> +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
>> @@ -329,7 +329,7 @@ int arch_cpu_init(void)
>>  	return 0;
>>  }
>>  
>> -#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
>> +#ifdef CONFIG_ARMV7_NONSEC
>>  /* Set the address at which the secondary core starts from.*/
>>  void smp_set_core_boot_addr(unsigned long addr, int corenr)
>>  {
>> diff --git a/arch/arm/cpu/armv7/virt-dt.c b/arch/arm/cpu/armv7/virt-dt.c
>> index 9408e33..caaaaab 100644
>> --- a/arch/arm/cpu/armv7/virt-dt.c
>> +++ b/arch/arm/cpu/armv7/virt-dt.c
>> @@ -90,7 +90,7 @@ static int fdt_psci(void *fdt)
>>  
>>  int psci_update_dt(void *fdt)
>>  {
>> -#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
>> +#ifdef CONFIG_ARMV7_NONSEC
> 
> This is redundant now, isn't it? We compile this file only if
> CONFIG_ARMV7_NONSEC is defined (see above).

Right, even better. I'll clean up on top unless this series requires
another round.

> 
> The rest of the patch looks OK to me.
> 
> Cheers,
> Andre.

Thanks,
Jan

-- 
Siemens AG, Corporate Technology, CT RTC ITP SES-DE
Corporate Competence Center Embedded Linux

[U-Boot] [PATCH v7 02/17] sun7i: Remove duplicate call to psci_arch_init

[Jan Kiszka]

This is already invoked a few cycles later in monitor mode by
_secure_monitor (_sunxi_cpu_entry calls _do_nonsec_entry which triggers
_secure_monitor via smc #0). Drop it here, it serves no purpose.

CC: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Tested-by: Ian Campbell <ijc@hellion.org.uk>
Tested-by: Hans de Goede <hdegoede@redhat.com>
---
 arch/arm/cpu/armv7/sunxi/psci.S | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S
index e0a524e..07b2d76 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.S
+++ b/arch/arm/cpu/armv7/sunxi/psci.S
@@ -254,7 +254,6 @@ _sunxi_cpu_entry:
 	isb
 
 	bl	_nonsec_init
-	bl	psci_arch_init
 
 	adr	r0, _target_pc
 	ldr	r0, [r0]
-- 
2.1.4

[U-Boot] [PATCH v7 03/17] ARM: Factor out common psci_get_cpu_id

[Jan Kiszka]

Will be required for obtaining the ID of the current CPU in shared PSCI
functions. The default implementation requires a dense ID space and only
supports a single cluster. Therefore, the functions can be overloaded in
cases where these assumptions do not hold.

CC: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Tested-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
---
 arch/arm/cpu/armv7/psci.S       |  8 ++++++++
 arch/arm/cpu/armv7/sunxi/psci.S | 12 +++++++-----
 2 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index bf11a34..12ad09b 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -99,4 +99,12 @@ _smc_psci:
 	pop	{r4-r7, lr}
 	movs	pc, lr			@ Return to the kernel
 
+@ Requires dense and single-cluster CPU ID space
+ENTRY(psci_get_cpu_id)
+	mrc	p15, 0, r0, c0, c0, 5	/* read MPIDR */
+	and	r0, r0, #0xff		/* return CPU ID in cluster */
+	bx	lr
+ENDPROC(psci_get_cpu_id)
+.weak psci_get_cpu_id
+
 	.popsection
diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S
index 07b2d76..bcc419d 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.S
+++ b/arch/arm/cpu/armv7/sunxi/psci.S
@@ -19,6 +19,7 @@
 
 #include <config.h>
 #include <asm/gic.h>
+#include <asm/macro.h>
 #include <asm/psci.h>
 #include <asm/arch/cpu.h>
 
@@ -290,6 +291,8 @@ psci_cpu_off:
 
 .globl	psci_arch_init
 psci_arch_init:
+	mov	r6, lr
+
 	movw	r4, #(GICD_BASE & 0xffff)
 	movt	r4, #(GICD_BASE >> 16)
 
@@ -315,18 +318,17 @@ psci_arch_init:
 	mcr	p15, 0, r5, c1, c1, 0	@ Write SCR
 	isb
 
-	mrc	p15, 0, r4, c0, c0, 5	@ MPIDR
-	and	r4, r4, #3		@ cpu number in cluster
+	bl	psci_get_cpu_id
 	mov	r5, #0x400		@ 1kB of stack per CPU
-	mul	r4, r4, r5
+	mul	r0, r0, r5
 
 	adr	r5, text_end		@ end of text
 	add	r5, r5, #0x2000		@ Skip two pages
 	lsr	r5, r5, #12		@ Align to start of page
 	lsl	r5, r5, #12
-	sub	sp, r5, r4		@ here's our stack!
+	sub	sp, r5, r0		@ here's our stack!
 
-	bx	lr
+	bx	r6
 
 text_end:
 	.popsection
-- 
2.1.4

[U-Boot] [PATCH v7 04/17] ARM: Factor out reusable psci_cpu_off_common

[Jan Kiszka]

Move parts of sunxi's psci_cpu_off into psci_cpu_off_common, namely
cache disabling and flushing, clrex and the disabling of SMP for the
dying CPU. These steps are apparently generic for ARMv7 and will be
reused for Tegra124 support.

As the way of disabled SMP is not architectural, though commonly done
via ACLTR, the related function can be overloaded.

CC: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Tested-by: Ian Campbell <ijc@hellion.org.uk>
---
 arch/arm/cpu/armv7/psci.S       | 77 +++++++++++++++++++++++++++++++++++++++++
 arch/arm/cpu/armv7/sunxi/psci.S | 63 +--------------------------------
 2 files changed, 78 insertions(+), 62 deletions(-)

diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index 12ad09b..cdcdccd 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -107,4 +107,81 @@ ENTRY(psci_get_cpu_id)
 ENDPROC(psci_get_cpu_id)
 .weak psci_get_cpu_id
 
+/* Imported from Linux kernel */
+LENTRY(v7_flush_dcache_all)
+	dmb					@ ensure ordering with previous memory accesses
+	mrc	p15, 1, r0, c0, c0, 1		@ read clidr
+	ands	r3, r0, #0x7000000		@ extract loc from clidr
+	mov	r3, r3, lsr #23			@ left align loc bit field
+	beq	finished			@ if loc is 0, then no need to clean
+	mov	r10, #0				@ start clean at cache level 0
+flush_levels:
+	add	r2, r10, r10, lsr #1		@ work out 3x current cache level
+	mov	r1, r0, lsr r2			@ extract cache type bits from clidr
+	and	r1, r1, #7			@ mask of the bits for current cache only
+	cmp	r1, #2				@ see what cache we have at this level
+	blt	skip				@ skip if no cache, or just i-cache
+	mrs     r9, cpsr			@ make cssr&csidr read atomic
+	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
+	isb					@ isb to sych the new cssr&csidr
+	mrc	p15, 1, r1, c0, c0, 0		@ read the new csidr
+	msr     cpsr_c, r9
+	and	r2, r1, #7			@ extract the length of the cache lines
+	add	r2, r2, #4			@ add 4 (line length offset)
+	ldr	r4, =0x3ff
+	ands	r4, r4, r1, lsr #3		@ find maximum number on the way size
+	clz	r5, r4				@ find bit position of way size increment
+	ldr	r7, =0x7fff
+	ands	r7, r7, r1, lsr #13		@ extract max number of the index size
+loop1:
+	mov	r9, r7				@ create working copy of max index
+loop2:
+	orr	r11, r10, r4, lsl r5		@ factor way and cache number into r11
+	orr	r11, r11, r9, lsl r2		@ factor index number into r11
+	mcr	p15, 0, r11, c7, c14, 2		@ clean & invalidate by set/way
+	subs	r9, r9, #1			@ decrement the index
+	bge	loop2
+	subs	r4, r4, #1			@ decrement the way
+	bge	loop1
+skip:
+	add	r10, r10, #2			@ increment cache number
+	cmp	r3, r10
+	bgt	flush_levels
+finished:
+	mov	r10, #0				@ swith back to cache level 0
+	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
+	dsb	st
+	isb
+	bx	lr
+ENDPROC(v7_flush_dcache_all)
+
+ENTRY(psci_disable_smp)
+	mrc	p15, 0, r0, c1, c0, 1		@ ACTLR
+	bic	r0, r0, #(1 << 6)		@ Clear SMP bit
+	mcr	p15, 0, r0, c1, c0, 1		@ ACTLR
+	isb
+	dsb
+	bx	lr
+ENDPROC(psci_disable_smp)
+.weak psci_disable_smp
+
+ENTRY(psci_cpu_off_common)
+	push	{lr}
+
+	mrc	p15, 0, r0, c1, c0, 0		@ SCTLR
+	bic	r0, r0, #(1 << 2)		@ Clear C bit
+	mcr	p15, 0, r0, c1, c0, 0		@ SCTLR
+	isb
+	dsb
+
+	bl	v7_flush_dcache_all
+
+	clrex					@ Why???
+
+	bl	psci_disable_smp
+
+	pop	{lr}
+	bx	lr
+ENDPROC(psci_cpu_off_common)
+
 	.popsection
diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S
index bcc419d..05d047b 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.S
+++ b/arch/arm/cpu/armv7/sunxi/psci.S
@@ -200,53 +200,6 @@ psci_cpu_on:
 _target_pc:
 	.word	0
 
-/* Imported from Linux kernel */
-v7_flush_dcache_all:
-	dmb					@ ensure ordering with previous memory accesses
-	mrc	p15, 1, r0, c0, c0, 1		@ read clidr
-	ands	r3, r0, #0x7000000		@ extract loc from clidr
-	mov	r3, r3, lsr #23			@ left align loc bit field
-	beq	finished			@ if loc is 0, then no need to clean
-	mov	r10, #0				@ start clean at cache level 0
-flush_levels:
-	add	r2, r10, r10, lsr #1		@ work out 3x current cache level
-	mov	r1, r0, lsr r2			@ extract cache type bits from clidr
-	and	r1, r1, #7			@ mask of the bits for current cache only
-	cmp	r1, #2				@ see what cache we have@this level
-	blt	skip				@ skip if no cache, or just i-cache
-	mrs     r9, cpsr			@ make cssr&csidr read atomic
-	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
-	isb					@ isb to sych the new cssr&csidr
-	mrc	p15, 1, r1, c0, c0, 0		@ read the new csidr
-	msr     cpsr_c, r9
-	and	r2, r1, #7			@ extract the length of the cache lines
-	add	r2, r2, #4			@ add 4 (line length offset)
-	ldr	r4, =0x3ff
-	ands	r4, r4, r1, lsr #3		@ find maximum number on the way size
-	clz	r5, r4				@ find bit position of way size increment
-	ldr	r7, =0x7fff
-	ands	r7, r7, r1, lsr #13		@ extract max number of the index size
-loop1:
-	mov	r9, r7				@ create working copy of max index
-loop2:
-	orr	r11, r10, r4, lsl r5		@ factor way and cache number into r11
-	orr	r11, r11, r9, lsl r2		@ factor index number into r11
-	mcr	p15, 0, r11, c7, c14, 2		@ clean & invalidate by set/way
-	subs	r9, r9, #1			@ decrement the index
-	bge	loop2
-	subs	r4, r4, #1			@ decrement the way
-	bge	loop1
-skip:
-	add	r10, r10, #2			@ increment cache number
-	cmp	r3, r10
-	bgt	flush_levels
-finished:
-	mov	r10, #0				@ swith back to cache level 0
-	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
-	dsb	st
-	isb
-	bx	lr
-
 _sunxi_cpu_entry:
 	@ Set SMP bit
 	mrc	p15, 0, r0, c1, c0, 1
@@ -262,21 +215,7 @@ _sunxi_cpu_entry:
 
 .globl	psci_cpu_off
 psci_cpu_off:
-	mrc	p15, 0, r0, c1, c0, 0		@ SCTLR
-	bic	r0, r0, #(1 << 2)		@ Clear C bit
-	mcr	p15, 0, r0, c1, c0, 0		@ SCTLR
-	isb
-	dsb
-
-	bl	v7_flush_dcache_all
-
-	clrex					@ Why???
-
-	mrc	p15, 0, r0, c1, c0, 1		@ ACTLR
-	bic	r0, r0, #(1 << 6)		@ Clear SMP bit
-	mcr	p15, 0, r0, c1, c0, 1		@ ACTLR
-	isb
-	dsb
+	bl	psci_cpu_off_common
 
 	@ Ask CPU0 to pull the rug...
 	movw	r0, #(GICD_BASE & 0xffff)
-- 
2.1.4

[U-Boot] [PATCH v7 05/17] ARM: Factor out reusable psci_cpu_entry

[Jan Kiszka]

_sunxi_cpu_entry can be converted completely into a reusable
psci_cpu_entry. Tegra124 will use it as well.

As with psci_disable_smp, also the enabling is designed to be overloaded
in cased SMP is not controlled via ACTLR.

CC: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Tested-by: Ian Campbell <ijc@hellion.org.uk>
---
 arch/arm/cpu/armv7/psci.S       | 23 +++++++++++++++++++++++
 arch/arm/cpu/armv7/sunxi/psci.S | 20 ++------------------
 2 files changed, 25 insertions(+), 18 deletions(-)

diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index cdcdccd..7d89b43 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -165,6 +165,15 @@ ENTRY(psci_disable_smp)
 ENDPROC(psci_disable_smp)
 .weak psci_disable_smp
 
+ENTRY(psci_enable_smp)
+	mrc	p15, 0, r0, c1, c0, 1		@ ACTLR
+	orr	r0, r0, #(1 << 6)		@ Set SMP bit
+	mcr	p15, 0, r0, c1, c0, 1		@ ACTLR
+	isb
+	bx	lr
+ENDPROC(psci_enable_smp)
+.weak psci_enable_smp
+
 ENTRY(psci_cpu_off_common)
 	push	{lr}
 
@@ -184,4 +193,18 @@ ENTRY(psci_cpu_off_common)
 	bx	lr
 ENDPROC(psci_cpu_off_common)
 
+ENTRY(psci_cpu_entry)
+	bl	psci_enable_smp
+
+	bl	_nonsec_init
+
+	adr	r0, _psci_target_pc
+	ldr	r0, [r0]
+	b	_do_nonsec_entry
+ENDPROC(psci_cpu_entry)
+
+.globl _psci_target_pc
+_psci_target_pc:
+	.word	0
+
 	.popsection
diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S
index 05d047b..90dcff1 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.S
+++ b/arch/arm/cpu/armv7/sunxi/psci.S
@@ -139,7 +139,7 @@ out:	mcr	p15, 0, r7, c1, c1, 0
 	@ r2 = target PC
 .globl	psci_cpu_on
 psci_cpu_on:
-	adr	r0, _target_pc
+	ldr	r0, =_psci_target_pc
 	str	r2, [r0]
 	dsb
 
@@ -151,7 +151,7 @@ psci_cpu_on:
 	mov	r4, #1
 	lsl	r4, r4, r1
 
-	adr	r6, _sunxi_cpu_entry
+	ldr	r6, =psci_cpu_entry
 	str	r6, [r0, #0x1a4] @ PRIVATE_REG (boot vector)
 
 	@ Assert reset on target CPU
@@ -197,22 +197,6 @@ psci_cpu_on:
 	mov	r0, #ARM_PSCI_RET_SUCCESS	@ Return PSCI_RET_SUCCESS
 	mov	pc, lr
 
-_target_pc:
-	.word	0
-
-_sunxi_cpu_entry:
-	@ Set SMP bit
-	mrc	p15, 0, r0, c1, c0, 1
-	orr	r0, r0, #0x40
-	mcr	p15, 0, r0, c1, c0, 1
-	isb
-
-	bl	_nonsec_init
-
-	adr	r0, _target_pc
-	ldr	r0, [r0]
-	b	_do_nonsec_entry
-
 .globl	psci_cpu_off
 psci_cpu_off:
 	bl	psci_cpu_off_common
-- 
2.1.4

[U-Boot] [PATCH v7 06/17] ARM: Factor out reusable psci_get_cpu_stack_top

[Jan Kiszka]

This algorithm will be useful on Tegra as well, plus we will need it for
making _psci_target_pc per-CPU.

CC: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Tested-by: Ian Campbell <ijc@hellion.org.uk>
---
 arch/arm/cpu/armv7/psci.S       | 14 ++++++++++++++
 arch/arm/cpu/armv7/sunxi/psci.S | 15 +++++----------
 2 files changed, 19 insertions(+), 10 deletions(-)

diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index 7d89b43..18d85c4 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -193,6 +193,20 @@ ENTRY(psci_cpu_off_common)
 	bx	lr
 ENDPROC(psci_cpu_off_common)
 
+@ expects CPU ID in r0 and returns stack top in r0
+ENTRY(psci_get_cpu_stack_top)
+	mov	r5, #0x400			@ 1kB of stack per CPU
+	mul	r0, r0, r5
+
+	ldr	r5, =psci_text_end		@ end of monitor text
+	add	r5, r5, #0x2000			@ Skip two pages
+	lsr	r5, r5, #12			@ Align to start of page
+	lsl	r5, r5, #12
+	sub	r0, r5, r0			@ here's our stack!
+
+	bx	lr
+ENDPROC(psci_get_cpu_stack_top)
+
 ENTRY(psci_cpu_entry)
 	bl	psci_enable_smp
 
diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S
index 90dcff1..dd583b2 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.S
+++ b/arch/arm/cpu/armv7/sunxi/psci.S
@@ -241,17 +241,12 @@ psci_arch_init:
 	mcr	p15, 0, r5, c1, c1, 0	@ Write SCR
 	isb
 
-	bl	psci_get_cpu_id
-	mov	r5, #0x400		@ 1kB of stack per CPU
-	mul	r0, r0, r5
-
-	adr	r5, text_end		@ end of text
-	add	r5, r5, #0x2000		@ Skip two pages
-	lsr	r5, r5, #12		@ Align to start of page
-	lsl	r5, r5, #12
-	sub	sp, r5, r0		@ here's our stack!
+	bl	psci_get_cpu_id		@ CPU ID => r0
+	bl	psci_get_cpu_stack_top	@ stack top => r0
+	mov	sp, r0
 
 	bx	r6
 
-text_end:
+	.globl psci_text_end
+psci_text_end:
 	.popsection
-- 
2.1.4

[U-Boot] [PATCH v7 07/17] ARM: Put target PC for PSCI CPU_ON on per-CPU stack

[Jan Kiszka]

Use a per-CPU variable for saving the target PC during CPU_ON
operations. This allows us to run this service independently on targets
that have more than 2 cores and also core-local power control.

CC: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Tested-by: Ian Campbell <ijc@hellion.org.uk>
---
 arch/arm/cpu/armv7/psci.S       | 11 +++++------
 arch/arm/cpu/armv7/sunxi/psci.S |  9 ++++++---
 2 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index 18d85c4..87c0c0b 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -17,6 +17,7 @@
 
 #include <config.h>
 #include <linux/linkage.h>
+#include <asm/macro.h>
 #include <asm/psci.h>
 
 	.pushsection ._secure.text, "ax"
@@ -202,6 +203,7 @@ ENTRY(psci_get_cpu_stack_top)
 	add	r5, r5, #0x2000			@ Skip two pages
 	lsr	r5, r5, #12			@ Align to start of page
 	lsl	r5, r5, #12
+	sub	r5, r5, #4			@ reserve 1 word for target PC
 	sub	r0, r5, r0			@ here's our stack!
 
 	bx	lr
@@ -212,13 +214,10 @@ ENTRY(psci_cpu_entry)
 
 	bl	_nonsec_init
 
-	adr	r0, _psci_target_pc
-	ldr	r0, [r0]
+	bl	psci_get_cpu_id			@ CPU ID => r0
+	bl	psci_get_cpu_stack_top		@ stack top => r0
+	ldr	r0, [r0]			@ target PC at stack top
 	b	_do_nonsec_entry
 ENDPROC(psci_cpu_entry)
 
-.globl _psci_target_pc
-_psci_target_pc:
-	.word	0
-
 	.popsection
diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S
index dd583b2..7ec0500 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.S
+++ b/arch/arm/cpu/armv7/sunxi/psci.S
@@ -139,8 +139,11 @@ out:	mcr	p15, 0, r7, c1, c1, 0
 	@ r2 = target PC
 .globl	psci_cpu_on
 psci_cpu_on:
-	ldr	r0, =_psci_target_pc
-	str	r2, [r0]
+	push	{lr}
+
+	mov	r0, r1
+	bl	psci_get_cpu_stack_top	@ get stack top of target CPU
+	str	r2, [r0]		@ store target PC at stack top
 	dsb
 
 	movw	r0, #(SUN7I_CPUCFG_BASE & 0xffff)
@@ -195,7 +198,7 @@ psci_cpu_on:
 	str	r6, [r0, #0x1e4]
 
 	mov	r0, #ARM_PSCI_RET_SUCCESS	@ Return PSCI_RET_SUCCESS
-	mov	pc, lr
+	pop	{pc}
 
 .globl	psci_cpu_off
 psci_cpu_off:
-- 
2.1.4

[U-Boot] [PATCH v7 07/17] ARM: Put target PC for PSCI CPU_ON on per-CPU stack

[Wang Dongsheng]

> -----Original Message-----
> From: U-Boot [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Jan Kiszka
> Sent: Tuesday, April 21, 2015 1:19 PM
> To: U-Boot Mailing List; Tom Rini
> Cc: Marc Zyngier; Tom Warren; Paul Walmsley; Ian Campbell; Thierry Reding
> Subject: [U-Boot] [PATCH v7 07/17] ARM: Put target PC for PSCI CPU_ON on per-CPU
> stack
> 
> Use a per-CPU variable for saving the target PC during CPU_ON operations. This
> allows us to run this service independently on targets that have more than 2
> cores and also core-local power control.
> 
> CC: Marc Zyngier <marc.zyngier@arm.com>
> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
> Reviewed-by: Tom Rini <trini@konsulko.com>
> Reviewed-by: Thierry Reding <treding@nvidia.com>
> Tested-by: Thierry Reding <treding@nvidia.com>
> Tested-by: Ian Campbell <ijc@hellion.org.uk>
> ---
>  arch/arm/cpu/armv7/psci.S       | 11 +++++------
>  arch/arm/cpu/armv7/sunxi/psci.S |  9 ++++++---
>  2 files changed, 11 insertions(+), 9 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S index
> 18d85c4..87c0c0b 100644
> --- a/arch/arm/cpu/armv7/psci.S
> +++ b/arch/arm/cpu/armv7/psci.S
> @@ -17,6 +17,7 @@
> 
>  #include <config.h>
>  #include <linux/linkage.h>
> +#include <asm/macro.h>
>  #include <asm/psci.h>
> 
>  	.pushsection ._secure.text, "ax"
> @@ -202,6 +203,7 @@ ENTRY(psci_get_cpu_stack_top)
>  	add	r5, r5, #0x2000			@ Skip two pages
>  	lsr	r5, r5, #12			@ Align to start of page
>  	lsl	r5, r5, #12
> +	sub	r5, r5, #4			@ reserve 1 word for target PC
>  	sub	r0, r5, r0			@ here's our stack!
> 
>  	bx	lr
> @@ -212,13 +214,10 @@ ENTRY(psci_cpu_entry)
> 
>  	bl	_nonsec_init
> 
> -	adr	r0, _psci_target_pc
> -	ldr	r0, [r0]
> +	bl	psci_get_cpu_id			@ CPU ID => r0
> +	bl	psci_get_cpu_stack_top		@ stack top => r0
> +	ldr	r0, [r0]			@ target PC at stack top
>  	b	_do_nonsec_entry
>  ENDPROC(psci_cpu_entry)
> 
> -.globl _psci_target_pc
> -_psci_target_pc:
> -	.word	0
> -
>  	.popsection
> diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S
> index dd583b2..7ec0500 100644
> --- a/arch/arm/cpu/armv7/sunxi/psci.S
> +++ b/arch/arm/cpu/armv7/sunxi/psci.S
> @@ -139,8 +139,11 @@ out:	mcr	p15, 0, r7, c1, c1, 0
>  	@ r2 = target PC
>  .globl	psci_cpu_on
>  psci_cpu_on:
> -	ldr	r0, =_psci_target_pc
> -	str	r2, [r0]
> +	push	{lr}
> +
> +	mov	r0, r1
> +	bl	psci_get_cpu_stack_top	@ get stack top of target CPU
> +	str	r2, [r0]		@ store target PC at stack top

Base on target PC will be saved in stack. The cpu(r1) should be mask firstly.
Because r1 value is 0xf0x, and it is not what we expected cpu value(0x1 or ...).
If not, the stack address is incorrect.

When I develop LS1021a PSCI code, I found this issue. So I think sunxi also has this
issue.

http://patchwork.ozlabs.org/patch/471695/

Regards,
-Dongsheng

[U-Boot] [PATCH v7 07/17] ARM: Put target PC for PSCI CPU_ON on per-CPU stack

[Jan Kiszka]

On 2015-05-13 09:21, Wang Dongsheng wrote:
> 
> 
>> -----Original Message-----
>> From: U-Boot [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Jan Kiszka
>> Sent: Tuesday, April 21, 2015 1:19 PM
>> To: U-Boot Mailing List; Tom Rini
>> Cc: Marc Zyngier; Tom Warren; Paul Walmsley; Ian Campbell; Thierry Reding
>> Subject: [U-Boot] [PATCH v7 07/17] ARM: Put target PC for PSCI CPU_ON on per-CPU
>> stack
>>
>> Use a per-CPU variable for saving the target PC during CPU_ON operations. This
>> allows us to run this service independently on targets that have more than 2
>> cores and also core-local power control.
>>
>> CC: Marc Zyngier <marc.zyngier@arm.com>
>> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
>> Reviewed-by: Tom Rini <trini@konsulko.com>
>> Reviewed-by: Thierry Reding <treding@nvidia.com>
>> Tested-by: Thierry Reding <treding@nvidia.com>
>> Tested-by: Ian Campbell <ijc@hellion.org.uk>
>> ---
>>  arch/arm/cpu/armv7/psci.S       | 11 +++++------
>>  arch/arm/cpu/armv7/sunxi/psci.S |  9 ++++++---
>>  2 files changed, 11 insertions(+), 9 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S index
>> 18d85c4..87c0c0b 100644
>> --- a/arch/arm/cpu/armv7/psci.S
>> +++ b/arch/arm/cpu/armv7/psci.S
>> @@ -17,6 +17,7 @@
>>
>>  #include <config.h>
>>  #include <linux/linkage.h>
>> +#include <asm/macro.h>
>>  #include <asm/psci.h>
>>
>>  	.pushsection ._secure.text, "ax"
>> @@ -202,6 +203,7 @@ ENTRY(psci_get_cpu_stack_top)
>>  	add	r5, r5, #0x2000			@ Skip two pages
>>  	lsr	r5, r5, #12			@ Align to start of page
>>  	lsl	r5, r5, #12
>> +	sub	r5, r5, #4			@ reserve 1 word for target PC
>>  	sub	r0, r5, r0			@ here's our stack!
>>
>>  	bx	lr
>> @@ -212,13 +214,10 @@ ENTRY(psci_cpu_entry)
>>
>>  	bl	_nonsec_init
>>
>> -	adr	r0, _psci_target_pc
>> -	ldr	r0, [r0]
>> +	bl	psci_get_cpu_id			@ CPU ID => r0
>> +	bl	psci_get_cpu_stack_top		@ stack top => r0
>> +	ldr	r0, [r0]			@ target PC at stack top
>>  	b	_do_nonsec_entry
>>  ENDPROC(psci_cpu_entry)
>>
>> -.globl _psci_target_pc
>> -_psci_target_pc:
>> -	.word	0
>> -
>>  	.popsection
>> diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S
>> index dd583b2..7ec0500 100644
>> --- a/arch/arm/cpu/armv7/sunxi/psci.S
>> +++ b/arch/arm/cpu/armv7/sunxi/psci.S
>> @@ -139,8 +139,11 @@ out:	mcr	p15, 0, r7, c1, c1, 0
>>  	@ r2 = target PC
>>  .globl	psci_cpu_on
>>  psci_cpu_on:
>> -	ldr	r0, =_psci_target_pc
>> -	str	r2, [r0]
>> +	push	{lr}
>> +
>> +	mov	r0, r1
>> +	bl	psci_get_cpu_stack_top	@ get stack top of target CPU
>> +	str	r2, [r0]		@ store target PC at stack top
> 
> Base on target PC will be saved in stack. The cpu(r1) should be mask firstly.
> Because r1 value is 0xf0x, and it is not what we expected cpu value(0x1 or ...).
> If not, the stack address is incorrect.
> 
> When I develop LS1021a PSCI code, I found this issue. So I think sunxi also has this
> issue.

IIRC, sunxi has no clusters != 0 so far, but you are right conceptually.
We already mask elsewhere in that function, so the instruction should
simply be moved up here.

Jan

-- 
Siemens AG, Corporate Technology, CT RTC ITP SES-DE
Corporate Competence Center Embedded Linux

[U-Boot] [PATCH v7 07/17] ARM: Put target PC for PSCI CPU_ON on per-CPU stack

[Wang Dongsheng]

> -----Original Message-----
> From: Jan Kiszka [mailto:jan.kiszka at siemens.com]
> Sent: Wednesday, May 13, 2015 3:31 PM
> To: Wang Dongsheng-B40534; U-Boot Mailing List; Tom Rini
> Cc: Marc Zyngier; Tom Warren; Paul Walmsley; Ian Campbell; Thierry Reding
> Subject: Re: [U-Boot] [PATCH v7 07/17] ARM: Put target PC for PSCI CPU_ON on
> per-CPU stack
> 
> On 2015-05-13 09:21, Wang Dongsheng wrote:
> >
> >
> >> -----Original Message-----
> >> From: U-Boot [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Jan
> >> Kiszka
> >> Sent: Tuesday, April 21, 2015 1:19 PM
> >> To: U-Boot Mailing List; Tom Rini
> >> Cc: Marc Zyngier; Tom Warren; Paul Walmsley; Ian Campbell; Thierry
> >> Reding
> >> Subject: [U-Boot] [PATCH v7 07/17] ARM: Put target PC for PSCI CPU_ON
> >> on per-CPU stack
> >>
> >> Use a per-CPU variable for saving the target PC during CPU_ON
> >> operations. This allows us to run this service independently on
> >> targets that have more than 2 cores and also core-local power control.
> >>
> >> CC: Marc Zyngier <marc.zyngier@arm.com>
> >> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
> >> Reviewed-by: Tom Rini <trini@konsulko.com>
> >> Reviewed-by: Thierry Reding <treding@nvidia.com>
> >> Tested-by: Thierry Reding <treding@nvidia.com>
> >> Tested-by: Ian Campbell <ijc@hellion.org.uk>
> >> ---
> >>  arch/arm/cpu/armv7/psci.S       | 11 +++++------
> >>  arch/arm/cpu/armv7/sunxi/psci.S |  9 ++++++---
> >>  2 files changed, 11 insertions(+), 9 deletions(-)
> >>
> >> diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
> >> index 18d85c4..87c0c0b 100644
> >> --- a/arch/arm/cpu/armv7/psci.S
> >> +++ b/arch/arm/cpu/armv7/psci.S
> >> @@ -17,6 +17,7 @@
> >>
> >>  #include <config.h>
> >>  #include <linux/linkage.h>
> >> +#include <asm/macro.h>
> >>  #include <asm/psci.h>
> >>
> >>  	.pushsection ._secure.text, "ax"
> >> @@ -202,6 +203,7 @@ ENTRY(psci_get_cpu_stack_top)
> >>  	add	r5, r5, #0x2000			@ Skip two pages
> >>  	lsr	r5, r5, #12			@ Align to start of page
> >>  	lsl	r5, r5, #12
> >> +	sub	r5, r5, #4			@ reserve 1 word for target PC
> >>  	sub	r0, r5, r0			@ here's our stack!
> >>
> >>  	bx	lr
> >> @@ -212,13 +214,10 @@ ENTRY(psci_cpu_entry)
> >>
> >>  	bl	_nonsec_init
> >>
> >> -	adr	r0, _psci_target_pc
> >> -	ldr	r0, [r0]
> >> +	bl	psci_get_cpu_id			@ CPU ID => r0
> >> +	bl	psci_get_cpu_stack_top		@ stack top => r0
> >> +	ldr	r0, [r0]			@ target PC at stack top
> >>  	b	_do_nonsec_entry
> >>  ENDPROC(psci_cpu_entry)
> >>
> >> -.globl _psci_target_pc
> >> -_psci_target_pc:
> >> -	.word	0
> >> -
> >>  	.popsection
> >> diff --git a/arch/arm/cpu/armv7/sunxi/psci.S
> >> b/arch/arm/cpu/armv7/sunxi/psci.S index dd583b2..7ec0500 100644
> >> --- a/arch/arm/cpu/armv7/sunxi/psci.S
> >> +++ b/arch/arm/cpu/armv7/sunxi/psci.S
> >> @@ -139,8 +139,11 @@ out:	mcr	p15, 0, r7, c1, c1, 0
> >>  	@ r2 = target PC
> >>  .globl	psci_cpu_on
> >>  psci_cpu_on:
> >> -	ldr	r0, =_psci_target_pc
> >> -	str	r2, [r0]
> >> +	push	{lr}
> >> +
> >> +	mov	r0, r1
> >> +	bl	psci_get_cpu_stack_top	@ get stack top of target CPU
> >> +	str	r2, [r0]		@ store target PC at stack top
> >
> > Base on target PC will be saved in stack. The cpu(r1) should be mask firstly.
> > Because r1 value is 0xf0x, and it is not what we expected cpu value(0x1
> or ...).
> > If not, the stack address is incorrect.
> >
> > When I develop LS1021a PSCI code, I found this issue. So I think sunxi
> > also has this issue.
> 
> IIRC, sunxi has no clusters != 0 so far, but you are right conceptually.

I don't know much about the sunxi platform. If I missed something please let me know.

The sunxi code also mask r1. So I guess the r1 the high of low-half word is also
not clear for sunxi platform.

        @ CPU mask
        and     r1, r1, #3      @ only care about first cluster
        mov     r4, #1
        lsl     r4, r4, r1

> We already mask elsewhere in that function, so the instruction should simply be
> moved up here.

Yes, psci_arch_init has mask for bootcpu, but there is should mask for cpu1 or... and
the stack is for target cpu. There is not for bootcpu stack.

Regards,
-Dongsheng

[U-Boot] [PATCH v7 08/17] tegra124: Add more registers to struct mc_ctlr

[Jan Kiszka]

From: Ian Campbell <ijc@hellion.org.uk>

I will need mc_security_cfg0/1 in a future patch and I added the rest while
debugging, so thought I might as well commit them.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Tested-by: Ian Campbell <ijc@hellion.org.uk>
---
 arch/arm/include/asm/arch-tegra124/mc.h | 35 +++++++++++++++++++++++++++++++--
 1 file changed, 33 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-tegra124/mc.h b/arch/arm/include/asm/arch-tegra124/mc.h
index d526dfe..5557732 100644
--- a/arch/arm/include/asm/arch-tegra124/mc.h
+++ b/arch/arm/include/asm/arch-tegra124/mc.h
@@ -35,9 +35,40 @@ struct mc_ctlr {
 	u32 mc_emem_adr_cfg;			/* offset 0x54 */
 	u32 mc_emem_adr_cfg_dev0;		/* offset 0x58 */
 	u32 mc_emem_adr_cfg_dev1;		/* offset 0x5C */
-	u32 reserved3[12];			/* offset 0x60 - 0x8C */
+	u32 reserved3[4];			/* offset 0x60 - 0x6C */
+	u32 mc_security_cfg0;			/* offset 0x70 */
+	u32 mc_security_cfg1;			/* offset 0x74 */
+	u32 reserved4[6];			/* offset 0x7C - 0x8C */
 	u32 mc_emem_arb_reserved[28];		/* offset 0x90 - 0xFC */
-	u32 reserved4[338];			/* offset 0x100 - 0x644 */
+	u32 reserved5[74];			/* offset 0x100 - 0x224 */
+	u32 mc_smmu_translation_enable_0;	/* offset 0x228 */
+	u32 mc_smmu_translation_enable_1;	/* offset 0x22C */
+	u32 mc_smmu_translation_enable_2;	/* offset 0x230 */
+	u32 mc_smmu_translation_enable_3;	/* offset 0x234 */
+	u32 mc_smmu_afi_asid;			/* offset 0x238 */
+	u32 mc_smmu_avpc_asid;			/* offset 0x23C */
+	u32 mc_smmu_dc_asid;			/* offset 0x240 */
+	u32 mc_smmu_dcb_asid;			/* offset 0x244 */
+	u32 reserved6[2];                       /* offset 0x248 - 0x24C */
+	u32 mc_smmu_hc_asid;			/* offset 0x250 */
+	u32 mc_smmu_hda_asid;			/* offset 0x254 */
+	u32 mc_smmu_isp2_asid;			/* offset 0x258 */
+	u32 reserved7[2];                       /* offset 0x25C - 0x260 */
+	u32 mc_smmu_msenc_asid;			/* offset 0x264 */
+	u32 mc_smmu_nv_asid;			/* offset 0x268 */
+	u32 mc_smmu_nv2_asid;			/* offset 0x26C */
+	u32 mc_smmu_ppcs_asid;			/* offset 0x270 */
+	u32 mc_smmu_sata_asid;			/* offset 0x274 */
+	u32 reserved8[1];                       /* offset 0x278 */
+	u32 mc_smmu_vde_asid;			/* offset 0x27C */
+	u32 mc_smmu_vi_asid;			/* offset 0x280 */
+	u32 mc_smmu_vic_asid;			/* offset 0x284 */
+	u32 mc_smmu_xusb_host_asid;		/* offset 0x288 */
+	u32 mc_smmu_xusb_dev_asid;		/* offset 0x28C */
+	u32 reserved9[1];                       /* offset 0x290 */
+	u32 mc_smmu_tsec_asid;			/* offset 0x294 */
+	u32 mc_smmu_ppcs1_asid;			/* offset 0x298 */
+	u32 reserved10[235];			/* offset 0x29C - 0x644 */
 	u32 mc_video_protect_bom;		/* offset 0x648 */
 	u32 mc_video_protect_size_mb;		/* offset 0x64c */
 	u32 mc_video_protect_reg_ctrl;		/* offset 0x650 */
-- 
2.1.4

[U-Boot] [PATCH v7 09/17] virt-dt: Allow reservation of secure region when in a RAM carveout

[Jan Kiszka]

In this case the secure code lives in RAM, and hence the memory node in
the device tree needs to be adjusted. This avoids that the OS will map
and possibly access the reservation.

Add support for setting CONFIG_ARMV7_SECURE_RESERVE_SIZE to carve out
such a region. We only support cutting off memory from the beginning or
the end of a RAM bank as we do not want to increase their number (which
would happen if punching a hole) for simplicity reasons

This will be used in a subsequent patch for Jetson-TK1.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
---
 arch/arm/cpu/armv7/virt-dt.c | 29 +++++++++++++++++++++++++++++
 arch/arm/include/asm/armv7.h |  1 +
 arch/arm/lib/bootm-fdt.c     |  6 ++++++
 3 files changed, 36 insertions(+)

diff --git a/arch/arm/cpu/armv7/virt-dt.c b/arch/arm/cpu/armv7/virt-dt.c
index caaaaab..32c368f 100644
--- a/arch/arm/cpu/armv7/virt-dt.c
+++ b/arch/arm/cpu/armv7/virt-dt.c
@@ -16,6 +16,7 @@
  */
 
 #include <common.h>
+#include <errno.h>
 #include <stdio_dev.h>
 #include <linux/ctype.h>
 #include <linux/types.h>
@@ -88,6 +89,34 @@ static int fdt_psci(void *fdt)
 	return 0;
 }
 
+int armv7_apply_memory_carveout(u64 *start, u64 *size)
+{
+#ifdef CONFIG_ARMV7_SECURE_RESERVE_SIZE
+	if (*start + *size < CONFIG_ARMV7_SECURE_BASE ||
+	    *start >= (u64)CONFIG_ARMV7_SECURE_BASE +
+		      CONFIG_ARMV7_SECURE_RESERVE_SIZE)
+		return 0;
+
+	/* carveout must be at the beginning or the end of the bank */
+	if (*start == CONFIG_ARMV7_SECURE_BASE ||
+	    *start + *size == (u64)CONFIG_ARMV7_SECURE_BASE +
+			      CONFIG_ARMV7_SECURE_RESERVE_SIZE) {
+		if (*size < CONFIG_ARMV7_SECURE_RESERVE_SIZE) {
+			debug("Secure monitor larger than RAM bank!?\n");
+			return -EINVAL;
+		}
+		*size -= CONFIG_ARMV7_SECURE_RESERVE_SIZE;
+		if (*start == CONFIG_ARMV7_SECURE_BASE)
+			*start += CONFIG_ARMV7_SECURE_RESERVE_SIZE;
+		return 0;
+	}
+	debug("Secure monitor not located@beginning or end of RAM bank\n");
+	return -EINVAL;
+#else /* !CONFIG_ARMV7_SECURE_RESERVE_SIZE */
+	return 0;
+#endif
+}
+
 int psci_update_dt(void *fdt)
 {
 #ifdef CONFIG_ARMV7_NONSEC
diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
index 2bb1253..33357db 100644
--- a/arch/arm/include/asm/armv7.h
+++ b/arch/arm/include/asm/armv7.h
@@ -124,6 +124,7 @@ void v7_outer_cache_inval_range(u32 start, u32 end);
 #ifdef CONFIG_ARMV7_NONSEC
 
 int armv7_init_nonsec(void);
+int armv7_apply_memory_carveout(u64 *start, u64 *size);
 bool armv7_boot_nonsec(void);
 
 /* defined in assembly file */
diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c
index 49ba691..0eb10a8 100644
--- a/arch/arm/lib/bootm-fdt.c
+++ b/arch/arm/lib/bootm-fdt.c
@@ -17,6 +17,7 @@
 
 #include <common.h>
 #include <fdt_support.h>
+#include <asm/armv7.h>
 #include <asm/psci.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -31,6 +32,11 @@ int arch_fixup_fdt(void *blob)
 	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
 		start[bank] = bd->bi_dram[bank].start;
 		size[bank] = bd->bi_dram[bank].size;
+#ifdef CONFIG_ARMV7_NONSEC
+		ret = armv7_apply_memory_carveout(&start[bank], &size[bank]);
+		if (ret)
+			return ret;
+#endif
 	}
 
 	ret = fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
-- 
2.1.4

[U-Boot] [PATCH v7 10/17] tegra: Make tegra_powergate_power_on public

[Jan Kiszka]

Will be used for unpowergating CPUs.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Tested-by: Ian Campbell <ijc@hellion.org.uk>
---
 arch/arm/include/asm/arch-tegra/powergate.h | 1 +
 arch/arm/mach-tegra/powergate.c             | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-tegra/powergate.h b/arch/arm/include/asm/arch-tegra/powergate.h
index 130b58b..2e491f1 100644
--- a/arch/arm/include/asm/arch-tegra/powergate.h
+++ b/arch/arm/include/asm/arch-tegra/powergate.h
@@ -33,6 +33,7 @@ enum tegra_powergate {
 
 int tegra_powergate_sequence_power_up(enum tegra_powergate id,
 				      enum periph_id periph);
+int tegra_powergate_power_on(enum tegra_powergate id);
 int tegra_powergate_power_off(enum tegra_powergate id);
 
 #endif
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index 439cff3..6331cd4 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -44,7 +44,7 @@ static int tegra_powergate_set(enum tegra_powergate id, bool state)
 	return -ETIMEDOUT;
 }
 
-static int tegra_powergate_power_on(enum tegra_powergate id)
+int tegra_powergate_power_on(enum tegra_powergate id)
 {
 	return tegra_powergate_set(id, true);
 }
-- 
2.1.4

[U-Boot] [PATCH v7 11/17] ARM: Add board-specific initialization hook for PSCI

[Jan Kiszka]

Tegra boards will have to initialize power management for the PSCI
support this way.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
---
 arch/arm/cpu/armv7/virt-v7.c | 6 ++++++
 arch/arm/include/asm/psci.h  | 1 +
 2 files changed, 7 insertions(+)

diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c
index 4cb8806..db4f6ad 100644
--- a/arch/arm/cpu/armv7/virt-v7.c
+++ b/arch/arm/cpu/armv7/virt-v7.c
@@ -75,6 +75,10 @@ void __weak smp_kick_all_cpus(void)
 	kick_secondary_cpus_gic(gic_dist_addr);
 }
 
+__weak void psci_board_init(void)
+{
+}
+
 int armv7_init_nonsec(void)
 {
 	unsigned int reg;
@@ -112,6 +116,8 @@ int armv7_init_nonsec(void)
 	for (i = 1; i <= itlinesnr; i++)
 		writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i);
 
+	psci_board_init();
+
 	/*
 	 * Relocate secure section before any cpu runs in secure ram.
 	 * smp_kick_all_cpus may enable other cores and runs into secure
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index 50a3ca4..128a606 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -34,6 +34,7 @@
 
 #ifndef __ASSEMBLY__
 int psci_update_dt(void *fdt);
+void psci_board_init(void);
 #endif /* ! __ASSEMBLY__ */
 
 #endif /* __ARM_PSCI_H__ */
-- 
2.1.4

[U-Boot] [PATCH v7 12/17] tegra124: Add PSCI support for Tegra124

[Jan Kiszka]

This is based on Thierry Reding's work and uses Ian Campell's
preparatory patches. It comes with full support for CPU_ON/OFF PSCI
services. The algorithm used in this version for turning CPUs on and
off was proposed by Peter De Schrijver and Thierry Reding in
http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/210881. It
consists of first enabling CPU1..3 via the PMC, just to powergate them
again with the help of the Flow Controller. Once the Flow Controller is
in place, we can leave the PMC alone while processing CPU_ON and CPU_OFF
PSCI requests.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
---
 arch/arm/include/asm/arch-tegra124/flow.h |   6 ++
 arch/arm/mach-tegra/Makefile              |   4 ++
 arch/arm/mach-tegra/psci.S                | 101 ++++++++++++++++++++++++++++++
 arch/arm/mach-tegra/tegra124/Makefile     |   4 ++
 arch/arm/mach-tegra/tegra124/psci.c       |  59 +++++++++++++++++
 5 files changed, 174 insertions(+)
 create mode 100644 arch/arm/mach-tegra/psci.S
 create mode 100644 arch/arm/mach-tegra/tegra124/psci.c

diff --git a/arch/arm/include/asm/arch-tegra124/flow.h b/arch/arm/include/asm/arch-tegra124/flow.h
index 0db1881..d6f515f 100644
--- a/arch/arm/include/asm/arch-tegra124/flow.h
+++ b/arch/arm/include/asm/arch-tegra124/flow.h
@@ -37,4 +37,10 @@ struct flow_ctlr {
 /* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */
 #define ACTIVE_LP		(1 << 0)
 
+/* CPUn_CSR_0 */
+#define CSR_ENABLE		(1 << 0)
+#define CSR_IMMEDIATE_WAKE	(1 << 3)
+#define CSR_WAIT_WFI_SHIFT	8
+#define CSR_PWR_OFF_STS		(1 << 16)
+
 #endif	/*  _TEGRA124_FLOW_H_ */
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 04cef0a..0779086 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -25,6 +25,10 @@ obj-y += xusb-padctl.o
 obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o
 obj-$(CONFIG_TEGRA124) += vpr.o
 
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_ARMV7_PSCI) += psci.o
+endif
+
 obj-$(CONFIG_TEGRA20) += tegra20/
 obj-$(CONFIG_TEGRA30) += tegra30/
 obj-$(CONFIG_TEGRA114) += tegra114/
diff --git a/arch/arm/mach-tegra/psci.S b/arch/arm/mach-tegra/psci.S
new file mode 100644
index 0000000..e4733e6
--- /dev/null
+++ b/arch/arm/mach-tegra/psci.S
@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) 2014, NVIDIA
+ * Copyright (C) 2015, Siemens AG
+ *
+ * Authors:
+ *  Thierry Reding <treding@nvidia.com>
+ *  Jan Kiszka <jan.kiszka@siemens.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/linkage.h>
+#include <asm/macro.h>
+#include <asm/psci.h>
+
+	.pushsection ._secure.text, "ax"
+	.arch_extension sec
+
+#define TEGRA_SB_CSR_0			0x6000c200
+#define NS_RST_VEC_WR_DIS		(1 << 1)
+
+#define TEGRA_RESET_EXCEPTION_VECTOR	0x6000f100
+
+#define TEGRA_FLOW_CTRL_BASE		0x60007000
+#define FLOW_CTRL_CPU_CSR		0x08
+#define CSR_ENABLE			(1 << 0)
+#define CSR_IMMEDIATE_WAKE		(1 << 3)
+#define CSR_WAIT_WFI_SHIFT		8
+#define FLOW_CTRL_CPU1_CSR		0x18
+
+@ converts CPU ID into FLOW_CTRL_CPUn_CSR offset
+.macro get_csr_reg cpu, ofs, tmp
+	cmp	\cpu, #0		@ CPU0?
+	lsl	\tmp, \cpu, #3	@ multiple by 8 (register offset CPU1-3)
+	moveq	\ofs, #FLOW_CTRL_CPU_CSR
+	addne	\ofs, \tmp, #FLOW_CTRL_CPU1_CSR - 8
+.endm
+
+ENTRY(psci_arch_init)
+	mov	r6, lr
+
+	mrc	p15, 0, r5, c1, c1, 0	@ Read SCR
+	bic	r5, r5, #1		@ Secure mode
+	mcr	p15, 0, r5, c1, c1, 0	@ Write SCR
+	isb
+
+	@ lock reset vector for non-secure
+	ldr	r4, =TEGRA_SB_CSR_0
+	ldr	r5, [r4]
+	orr	r5, r5, #NS_RST_VEC_WR_DIS
+	str	r5, [r4]
+
+	bl	psci_get_cpu_id		@ CPU ID => r0
+	bl	psci_get_cpu_stack_top	@ stack top => r0
+	mov	sp, r0
+
+	bx	r6
+ENDPROC(psci_arch_init)
+
+ENTRY(psci_cpu_off)
+	bl	psci_cpu_off_common
+
+	bl	psci_get_cpu_id		@ CPU ID => r0
+
+	get_csr_reg r0, r2, r3
+
+	ldr	r6, =TEGRA_FLOW_CTRL_BASE
+	mov	r5, #(CSR_ENABLE)
+	mov	r4, #(1 << CSR_WAIT_WFI_SHIFT)
+	add	r5, r4, lsl r0
+	str	r5, [r6, r2]
+
+_loop:	wfi
+	b	_loop
+ENDPROC(psci_cpu_off)
+
+ENTRY(psci_cpu_on)
+	push	{lr}
+
+	mov	r0, r1
+	bl	psci_get_cpu_stack_top	@ get stack top of target CPU
+	str	r2, [r0]		@ store target PC at stack top
+	dsb
+
+	ldr	r6, =TEGRA_RESET_EXCEPTION_VECTOR
+	ldr	r5, =psci_cpu_entry
+	str	r5, [r6]
+
+	get_csr_reg r1, r2, r3
+
+	ldr	r6, =TEGRA_FLOW_CTRL_BASE
+	mov	r5, #(CSR_IMMEDIATE_WAKE | CSR_ENABLE)
+	str	r5, [r6, r2]
+
+	mov	r0, #ARM_PSCI_RET_SUCCESS	@ Return PSCI_RET_SUCCESS
+	pop	{pc}
+ENDPROC(psci_cpu_on)
+
+	.globl psci_text_end
+psci_text_end:
+	.popsection
diff --git a/arch/arm/mach-tegra/tegra124/Makefile b/arch/arm/mach-tegra/tegra124/Makefile
index ef2da29..f577f45 100644
--- a/arch/arm/mach-tegra/tegra124/Makefile
+++ b/arch/arm/mach-tegra/tegra124/Makefile
@@ -11,3 +11,7 @@ obj-y	+= clock.o
 obj-y	+= funcmux.o
 obj-y	+= pinmux.o
 obj-y	+= xusb-padctl.o
+
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_ARMV7_NONSEC) += psci.o
+endif
diff --git a/arch/arm/mach-tegra/tegra124/psci.c b/arch/arm/mach-tegra/tegra124/psci.c
new file mode 100644
index 0000000..16d1965
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra124/psci.c
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2015, Siemens AG
+ * Author: Jan Kiszka <jan.kiszka@siemens.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/psci.h>
+#include <asm/arch/flow.h>
+#include <asm/arch/powergate.h>
+#include <asm/arch-tegra/ap.h>
+#include <asm/arch-tegra/pmc.h>
+
+static void park_cpu(void)
+{
+	while (1)
+		asm volatile("wfi");
+}
+
+/**
+ * Initialize power management for application processors
+ */
+void psci_board_init(void)
+{
+	struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
+
+	writel((u32)park_cpu, EXCEP_VECTOR_CPU_RESET_VECTOR);
+
+	/*
+	 * The naturally expected order of putting these CPUs under Flow
+	 * Controller regime would be
+	 *  - configure the Flow Controller
+	 *  - power up the CPUs
+	 *  - wait for the CPUs to hit wfi and be powered down again
+	 *
+	 * However, this doesn't work in practice. We rather need to power them
+	 * up first and park them in wfi. While they are waiting there, we can
+	 * indeed program the Flow Controller to powergate them on wfi, which
+	 * will then happen immediately as they are already in that state.
+	 */
+	tegra_powergate_power_on(TEGRA_POWERGATE_CPU1);
+	tegra_powergate_power_on(TEGRA_POWERGATE_CPU2);
+	tegra_powergate_power_on(TEGRA_POWERGATE_CPU3);
+
+	writel((2 << CSR_WAIT_WFI_SHIFT) | CSR_ENABLE, &flow->cpu1_csr);
+	writel((4 << CSR_WAIT_WFI_SHIFT) | CSR_ENABLE, &flow->cpu2_csr);
+	writel((8 << CSR_WAIT_WFI_SHIFT) | CSR_ENABLE, &flow->cpu3_csr);
+
+	writel(EVENT_MODE_STOP, &flow->halt_cpu1_events);
+	writel(EVENT_MODE_STOP, &flow->halt_cpu2_events);
+	writel(EVENT_MODE_STOP, &flow->halt_cpu3_events);
+
+	while (!(readl(&flow->cpu1_csr) & CSR_PWR_OFF_STS) ||
+		!(readl(&flow->cpu2_csr) & CSR_PWR_OFF_STS) ||
+		!(readl(&flow->cpu3_csr) & CSR_PWR_OFF_STS))
+		/* wait */;
+}
-- 
2.1.4

[U-Boot] [PATCH v7 13/17] tegra124: Reserve secure RAM using MC_SECURITY_CFG{0, 1}_0

[Jan Kiszka]

From: Ian Campbell <ijc@hellion.org.uk>

These registers can be used to prevent non-secure world from accessing a
megabyte aligned region of RAM, use them to protect the u-boot secure monitor
code.

At first I tried to do this from s_init(), however this inexplicably causes
u-boot's networking (e.g. DHCP) to fail, while networking under Linux was fine.

So instead I have added a new weak arch function protect_secure_section()
called from relocate_secure_section() and reserved the region there. This is
better overall since it defers the reservation until after the sec vs. non-sec
decision (which can be influenced by an envvar) has been made when booting the
os.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
[Jan: tiny style adjustment]
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Tested-by: Ian Campbell <ijc@hellion.org.uk>
---
 arch/arm/cpu/armv7/virt-v7.c  |  5 +++++
 arch/arm/include/asm/system.h |  1 +
 arch/arm/mach-tegra/ap.c      | 15 +++++++++++++++
 3 files changed, 21 insertions(+)

diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c
index db4f6ad..9c53306 100644
--- a/arch/arm/cpu/armv7/virt-v7.c
+++ b/arch/arm/cpu/armv7/virt-v7.c
@@ -46,6 +46,10 @@ static unsigned long get_gicd_base_address(void)
 #endif
 }
 
+/* Define a specific version of this function to enable any available
+ * hardware protections for the reserved region */
+void __weak protect_secure_section(void) {}
+
 static void relocate_secure_section(void)
 {
 #ifdef CONFIG_ARMV7_SECURE_BASE
@@ -54,6 +58,7 @@ static void relocate_secure_section(void)
 	memcpy((void *)CONFIG_ARMV7_SECURE_BASE, __secure_start, sz);
 	flush_dcache_range(CONFIG_ARMV7_SECURE_BASE,
 			   CONFIG_ARMV7_SECURE_BASE + sz + 1);
+	protect_secure_section();
 	invalidate_icache_all();
 #endif
 }
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 2a5bed2..d6dfddd 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -77,6 +77,7 @@ void armv8_switch_to_el1(void);
 void gic_init(void);
 void gic_send_sgi(unsigned long sgino);
 void wait_for_wakeup(void);
+void protect_secure_region(void);
 void smp_kick_all_cpus(void);
 
 void flush_l3_cache(void);
diff --git a/arch/arm/mach-tegra/ap.c b/arch/arm/mach-tegra/ap.c
index a17dfd1..869a2ed 100644
--- a/arch/arm/mach-tegra/ap.c
+++ b/arch/arm/mach-tegra/ap.c
@@ -10,6 +10,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/gp_padctrl.h>
+#include <asm/arch/mc.h>
 #include <asm/arch-tegra/ap.h>
 #include <asm/arch-tegra/clock.h>
 #include <asm/arch-tegra/fuse.h>
@@ -154,6 +155,20 @@ static void init_pmc_scratch(void)
 	writel(odmdata, &pmc->pmc_scratch20);
 }
 
+#ifdef CONFIG_ARMV7_SECURE_RESERVE_SIZE
+void protect_secure_section(void)
+{
+	struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
+
+	/* Must be MB aligned */
+	BUILD_BUG_ON(CONFIG_ARMV7_SECURE_BASE & 0xFFFFF);
+	BUILD_BUG_ON(CONFIG_ARMV7_SECURE_RESERVE_SIZE & 0xFFFFF);
+
+	writel(CONFIG_ARMV7_SECURE_BASE, &mc->mc_security_cfg0);
+	writel(CONFIG_ARMV7_SECURE_RESERVE_SIZE >> 20, &mc->mc_security_cfg1);
+}
+#endif
+
 void s_init(void)
 {
 	/* Init PMC scratch memory */
-- 
2.1.4

[U-Boot] [PATCH v7 14/17] tegra: Set CNTFRQ for secondary CPUs

[Jan Kiszka]

We only set CNTFRQ in arch_timer_init for the boot CPU. But this has to
happen for all cores.

Fixing this resolves problems of KVM with emulating the generic
timer/counter.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Tested-by: Ian Campbell <ijc@hellion.org.uk>
---
 arch/arm/mach-tegra/psci.S | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/mach-tegra/psci.S b/arch/arm/mach-tegra/psci.S
index e4733e6..b836da1 100644
--- a/arch/arm/mach-tegra/psci.S
+++ b/arch/arm/mach-tegra/psci.S
@@ -51,12 +51,25 @@ ENTRY(psci_arch_init)
 	str	r5, [r4]
 
 	bl	psci_get_cpu_id		@ CPU ID => r0
+
+	adr	r5, _sys_clock_freq
+	cmp	r0, #0
+
+	mrceq	p15, 0, r7, c14, c0, 0	@ read CNTFRQ from CPU0
+	streq	r7, [r5]
+
+	ldrne	r7, [r5]
+	mcrne	p15, 0, r7, c14, c0, 0	@ write CNTFRQ to CPU1..3
+
 	bl	psci_get_cpu_stack_top	@ stack top => r0
 	mov	sp, r0
 
 	bx	r6
 ENDPROC(psci_arch_init)
 
+_sys_clock_freq:
+	.word	0
+
 ENTRY(psci_cpu_off)
 	bl	psci_cpu_off_common
 
-- 
2.1.4

[U-Boot] [PATCH v7 15/17] ARM: tegra: Enable SMMU when going non-secure

[Jan Kiszka]

From: Thierry Reding <treding@nvidia.com>

Make sure to enable the SMMU when booting the kernel in non-secure mode.
This is necessary because some of the SMMU registers are restricted to
TrustZone-secured requestors, hence the kernel wouldn't be able to turn
the SMMU on. At the same time, enable translation for all memory clients
for the same reasons. The kernel will still be able to control SMMU IOVA
translation using the per-SWGROUP enable bits.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
---
 arch/arm/include/asm/arch-tegra124/mc.h |  2 ++
 arch/arm/mach-tegra/ap.c                | 40 +++++++++++++++++++++++++++++++++
 2 files changed, 42 insertions(+)

diff --git a/arch/arm/include/asm/arch-tegra124/mc.h b/arch/arm/include/asm/arch-tegra124/mc.h
index 5557732..37998a4 100644
--- a/arch/arm/include/asm/arch-tegra124/mc.h
+++ b/arch/arm/include/asm/arch-tegra124/mc.h
@@ -74,6 +74,8 @@ struct mc_ctlr {
 	u32 mc_video_protect_reg_ctrl;		/* offset 0x650 */
 };
 
+#define TEGRA_MC_SMMU_CONFIG_ENABLE (1 << 0)
+
 #define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED		(0 << 0)
 #define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED	(1 << 0)
 
diff --git a/arch/arm/mach-tegra/ap.c b/arch/arm/mach-tegra/ap.c
index 869a2ed..0b94e8a 100644
--- a/arch/arm/mach-tegra/ap.c
+++ b/arch/arm/mach-tegra/ap.c
@@ -169,6 +169,43 @@ void protect_secure_section(void)
 }
 #endif
 
+#if defined(CONFIG_ARMV7_NONSEC)
+static void smmu_flush(struct mc_ctlr *mc)
+{
+	(void)readl(&mc->mc_smmu_config);
+}
+
+static void smmu_enable(void)
+{
+	struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
+	u32 value;
+
+	/*
+	 * Enable translation for all clients since access to this register
+	 * is restricted to TrustZone-secured requestors. The kernel will use
+	 * the per-SWGROUP enable bits to enable or disable translations.
+	 */
+	writel(0xffffffff, &mc->mc_smmu_translation_enable_0);
+	writel(0xffffffff, &mc->mc_smmu_translation_enable_1);
+	writel(0xffffffff, &mc->mc_smmu_translation_enable_2);
+	writel(0xffffffff, &mc->mc_smmu_translation_enable_3);
+
+	/*
+	 * Enable SMMU globally since access to this register is restricted
+	 * to TrustZone-secured requestors.
+	 */
+	value = readl(&mc->mc_smmu_config);
+	value |= TEGRA_MC_SMMU_CONFIG_ENABLE;
+	writel(value, &mc->mc_smmu_config);
+
+	smmu_flush(mc);
+}
+#else
+static void smmu_enable(void)
+{
+}
+#endif
+
 void s_init(void)
 {
 	/* Init PMC scratch memory */
@@ -179,6 +216,9 @@ void s_init(void)
 	/* init the cache */
 	config_cache();
 
+	/* enable SMMU */
+	smmu_enable();
+
 	/* init vpr */
 	config_vpr();
 }
-- 
2.1.4

[U-Boot] [PATCH v7 16/17] tegra: Boot in non-secure mode by default

[Jan Kiszka]

Upstream Linux is broken with default configs when PSCI, thus non-secure
mode is enabled. So the user should explicitly enable this mode, e.g.
when she disabled CONFIG_CPU_IDLE in Linux (in which case it's safe to
use). We can revert this workaround once Linux got fixed.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
---
 arch/arm/cpu/armv7/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig
index 61e7c82..6c5d5dd 100644
--- a/arch/arm/cpu/armv7/Kconfig
+++ b/arch/arm/cpu/armv7/Kconfig
@@ -16,7 +16,7 @@ config ARMV7_NONSEC
 config ARMV7_BOOT_SEC_DEFAULT
 	boolean "Boot in secure mode by default" if EXPERT
 	depends on ARMV7_NONSEC
-	default n
+	default y if TEGRA
 	---help---
 	Say Y here to boot in secure mode by default even if non-secure mode
 	is supported. This option is useful to boot kernels which do not
-- 
2.1.4

[U-Boot] [PATCH v7 17/17] jetson-tk1: Add PSCI configuration options and reserve secure code

[Jan Kiszka]

From: Ian Campbell <ijc@hellion.org.uk>

The secure world code is relocated to the MB just below the top of 4G, we
reserve it in the FDT (by setting CONFIG_ARMV7_SECURE_RESERVE_SIZE) but it is
not protected in h/w. See next patch.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Tested-by: Ian Campbell <ijc@hellion.org.uk>
---
 arch/arm/mach-tegra/tegra124/Kconfig | 2 ++
 include/configs/jetson-tk1.h         | 5 +++++
 2 files changed, 7 insertions(+)

diff --git a/arch/arm/mach-tegra/tegra124/Kconfig b/arch/arm/mach-tegra/tegra124/Kconfig
index 88f627c..5114299 100644
--- a/arch/arm/mach-tegra/tegra124/Kconfig
+++ b/arch/arm/mach-tegra/tegra124/Kconfig
@@ -5,6 +5,8 @@ choice
 
 config TARGET_JETSON_TK1
 	bool "NVIDIA Tegra124 Jetson TK1 board"
+	select CPU_V7_HAS_NONSEC if !SPL_BUILD
+	select CPU_V7_HAS_VIRT if !SPL_BUILD
 
 config TARGET_NYAN_BIG
 	bool "Google/NVIDIA Nyan-big Chrombook"
diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h
index 8c016b7..aeafbd5 100644
--- a/include/configs/jetson-tk1.h
+++ b/include/configs/jetson-tk1.h
@@ -79,4 +79,9 @@
 #include "tegra-common-usb-gadget.h"
 #include "tegra-common-post.h"
 
+#define CONFIG_ARMV7_PSCI			1
+/* Reserve top 1M for secure RAM */
+#define CONFIG_ARMV7_SECURE_BASE		0xfff00000
+#define CONFIG_ARMV7_SECURE_RESERVE_SIZE	0x00100000
+
 #endif /* __CONFIG_H */
-- 
2.1.4

[U-Boot] [PATCH v7 17/17] jetson-tk1: Add PSCI configuration options and reserve secure code

[Ian Campbell]

On Tue, 2015-04-21 at 07:18 +0200, Jan Kiszka wrote:
> From: Ian Campbell <ijc@hellion.org.uk>
> 
> The secure world code is relocated to the MB just below the top of 4G, we
> reserve it in the FDT (by setting CONFIG_ARMV7_SECURE_RESERVE_SIZE) but it is
> not protected in h/w. See next patch.

Next patch, but this is the last one? Was it reordered earlier in the
series or is it not yet included here?

> 
> Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
> Reviewed-by: Tom Rini <trini@konsulko.com>
> Reviewed-by: Thierry Reding <treding@nvidia.com>
> Tested-by: Thierry Reding <treding@nvidia.com>
> Tested-by: Ian Campbell <ijc@hellion.org.uk>
> ---
>  arch/arm/mach-tegra/tegra124/Kconfig | 2 ++
>  include/configs/jetson-tk1.h         | 5 +++++
>  2 files changed, 7 insertions(+)
> 
> diff --git a/arch/arm/mach-tegra/tegra124/Kconfig b/arch/arm/mach-tegra/tegra124/Kconfig
> index 88f627c..5114299 100644
> --- a/arch/arm/mach-tegra/tegra124/Kconfig
> +++ b/arch/arm/mach-tegra/tegra124/Kconfig
> @@ -5,6 +5,8 @@ choice
>  
>  config TARGET_JETSON_TK1
>  	bool "NVIDIA Tegra124 Jetson TK1 board"
> +	select CPU_V7_HAS_NONSEC if !SPL_BUILD
> +	select CPU_V7_HAS_VIRT if !SPL_BUILD
>  
>  config TARGET_NYAN_BIG
>  	bool "Google/NVIDIA Nyan-big Chrombook"
> diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h
> index 8c016b7..aeafbd5 100644
> --- a/include/configs/jetson-tk1.h
> +++ b/include/configs/jetson-tk1.h
> @@ -79,4 +79,9 @@
>  #include "tegra-common-usb-gadget.h"
>  #include "tegra-common-post.h"
>  
> +#define CONFIG_ARMV7_PSCI			1
> +/* Reserve top 1M for secure RAM */
> +#define CONFIG_ARMV7_SECURE_BASE		0xfff00000
> +#define CONFIG_ARMV7_SECURE_RESERVE_SIZE	0x00100000
> +
>  #endif /* __CONFIG_H */

[U-Boot] [PATCH v7 17/17] jetson-tk1: Add PSCI configuration options and reserve secure code

[Jan Kiszka]

On 2015-04-21 19:58, Ian Campbell wrote:
> On Tue, 2015-04-21 at 07:18 +0200, Jan Kiszka wrote:
>> From: Ian Campbell <ijc@hellion.org.uk>
>>
>> The secure world code is relocated to the MB just below the top of 4G, we
>> reserve it in the FDT (by setting CONFIG_ARMV7_SECURE_RESERVE_SIZE) but it is
>> not protected in h/w. See next patch.
> 
> Next patch, but this is the last one? Was it reordered earlier in the
> series or is it not yet included here?

Yes, I reordered because this one activates the feature. Tom, in case
you apply, please just drop that reference.

Jan

> 
>>
>> Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
>> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
>> Reviewed-by: Tom Rini <trini@konsulko.com>
>> Reviewed-by: Thierry Reding <treding@nvidia.com>
>> Tested-by: Thierry Reding <treding@nvidia.com>
>> Tested-by: Ian Campbell <ijc@hellion.org.uk>
>> ---
>>  arch/arm/mach-tegra/tegra124/Kconfig | 2 ++
>>  include/configs/jetson-tk1.h         | 5 +++++
>>  2 files changed, 7 insertions(+)
>>
>> diff --git a/arch/arm/mach-tegra/tegra124/Kconfig b/arch/arm/mach-tegra/tegra124/Kconfig
>> index 88f627c..5114299 100644
>> --- a/arch/arm/mach-tegra/tegra124/Kconfig
>> +++ b/arch/arm/mach-tegra/tegra124/Kconfig
>> @@ -5,6 +5,8 @@ choice
>>  
>>  config TARGET_JETSON_TK1
>>  	bool "NVIDIA Tegra124 Jetson TK1 board"
>> +	select CPU_V7_HAS_NONSEC if !SPL_BUILD
>> +	select CPU_V7_HAS_VIRT if !SPL_BUILD
>>  
>>  config TARGET_NYAN_BIG
>>  	bool "Google/NVIDIA Nyan-big Chrombook"
>> diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h
>> index 8c016b7..aeafbd5 100644
>> --- a/include/configs/jetson-tk1.h
>> +++ b/include/configs/jetson-tk1.h
>> @@ -79,4 +79,9 @@
>>  #include "tegra-common-usb-gadget.h"
>>  #include "tegra-common-post.h"
>>  
>> +#define CONFIG_ARMV7_PSCI			1
>> +/* Reserve top 1M for secure RAM */
>> +#define CONFIG_ARMV7_SECURE_BASE		0xfff00000
>> +#define CONFIG_ARMV7_SECURE_RESERVE_SIZE	0x00100000
>> +
>>  #endif /* __CONFIG_H */
> 
> 

-- 
Siemens AG, Corporate Technology, CT RTC ITP SES-DE
Corporate Competence Center Embedded Linux

[U-Boot] [PATCH v7 00/17] Add PSCI support for Jetson TK1/Tegra124 + CNTFRQ fix

[Stephen Warren]

On 04/20/2015 11:18 PM, Jan Kiszka wrote:
> Changes in v7:
>   - rebased over master
>   - fixed issue that prevented secure boot with all cores
>     => replace ap_pm_init with psci_board_init hook
>   - enable CONFIG_ARMV7_BOOT_SEC_DEFAULT for tegra to avoid problems with
>     default config of current Linux
>   - add cleanup patch for CONFIG_ARMV7_NONSEC/VIRT/PSCI
>
> Note that I've removed reviewed and tested tags from modified patches.

The series,
Tested-by: Stephen Warren <swarren@nvidia.com>

I tested:

* With $bootm_boot_mode both unset, and set to "sec", my old kernel 
(which doesn't work in NS mode) still works.

* With $bootm_boot_mode set to "nonsec", my old kernel boots in HYP mode 
with virtualization extensions available, but of course hangs since the 
kernel isn't fixed to work in NS mode.

So, this series is both backwards compatible and seems to enable 
virtualization as desired.

I very briefly glanced through the code and didn't see anything that I'd 
want to say no too, but didn't really read it closely enough to say I've 
reviewed/ack'd it; I assume TomW/Thierry would give it a more thorough look.

[U-Boot] [PATCH v7 00/17] Add PSCI support for Jetson TK1/Tegra124 + CNTFRQ fix

[Jan Kiszka]

On 2015-04-21 07:18, Jan Kiszka wrote:
> Changes in v7:
>  - rebased over master
>  - fixed issue that prevented secure boot with all cores
>    => replace ap_pm_init with psci_board_init hook
>  - enable CONFIG_ARMV7_BOOT_SEC_DEFAULT for tegra to avoid problems with
>    default config of current Linux
>  - add cleanup patch for CONFIG_ARMV7_NONSEC/VIRT/PSCI
> 
> Note that I've removed reviewed and tested tags from modified patches.
> 

Tom, there were only trivial remarks regarding this series, and it still
applies on master. Do you plan to merge it? Or should I resend,
addressing them?

Jan

-- 
Siemens AG, Corporate Technology, CT RTC ITP SES-DE
Corporate Competence Center Embedded Linux

[U-Boot] [PATCH v7 00/17] Add PSCI support for Jetson TK1/Tegra124 + CNTFRQ fix

[Tom Warren]

Sorry, Jan.  Too many unmaskable interrupts lately ;).  I'll take a look today - if it applies OK to u-boot-tegra/master and builds OK, I'll try to get a PR out to Tom/Albert first thing next week.

Tom

> -----Original Message-----
> From: Jan Kiszka [mailto:jan.kiszka at siemens.com]
> Sent: Thursday, May 07, 2015 11:01 PM
> To: U-Boot Mailing List; Tom Rini
> Cc: Marc Zyngier; Steve Rae; Andre Przywara; Tom Warren; Paul Walmsley; Ian
> Campbell; Thierry Reding; York Sun
> Subject: Re: [PATCH v7 00/17] Add PSCI support for Jetson TK1/Tegra124 +
> CNTFRQ fix
> 
> On 2015-04-21 07:18, Jan Kiszka wrote:
> > Changes in v7:
> >  - rebased over master
> >  - fixed issue that prevented secure boot with all cores
> >    => replace ap_pm_init with psci_board_init hook
> >  - enable CONFIG_ARMV7_BOOT_SEC_DEFAULT for tegra to avoid problems
> with
> >    default config of current Linux
> >  - add cleanup patch for CONFIG_ARMV7_NONSEC/VIRT/PSCI
> >
> > Note that I've removed reviewed and tested tags from modified patches.
> >
> 
> Tom, there were only trivial remarks regarding this series, and it still applies on
> master. Do you plan to merge it? Or should I resend, addressing them?
> 
> Jan
> 
> --
> Siemens AG, Corporate Technology, CT RTC ITP SES-DE Corporate Competence
> Center Embedded Linux
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