[U-Boot] [PATCH 1/2][v2] pci/layerscape: remove unnecessary pcie_layerscape.h

[U-Boot] [PATCH 1/2][v2] pci/layerscape: remove unnecessary pcie_layerscape.h

[Minghuan Lian]

The patch uses the common function name ft_pci_setup to replace
ft_pcie_setup, then removes unnecessary pcie_layerscape.h because
all the functions have been declared in common.h.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
---
change log:
v1-v2: remove unnecessary pcie_layerscape.h

 arch/arm/include/asm/pcie_layerscape.h  | 13 -------------
 board/freescale/ls1021aqds/ls1021aqds.c |  5 ++---
 board/freescale/ls1021atwr/ls1021atwr.c |  5 ++---
 drivers/pci/pcie_layerscape.c           |  5 ++---
 4 files changed, 6 insertions(+), 22 deletions(-)
 delete mode 100644 arch/arm/include/asm/pcie_layerscape.h

diff --git a/arch/arm/include/asm/pcie_layerscape.h b/arch/arm/include/asm/pcie_layerscape.h
deleted file mode 100644
index fb08578..0000000
--- a/arch/arm/include/asm/pcie_layerscape.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __PCIE_LAYERSCAPE_H_
-#define __PCIE_LAYERSCAPE_H_
-
-void pci_init_board(void);
-void ft_pcie_setup(void *blob, bd_t *bd);
-
-#endif
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index 722b88f..bcd4361 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -12,7 +12,6 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/fsl_serdes.h>
 #include <asm/arch/ls102xa_stream_id.h>
-#include <asm/pcie_layerscape.h>
 #include <hwconfig.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
@@ -595,8 +594,8 @@ int ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
 
-#ifdef CONFIG_PCIE_LAYERSCAPE
-	ft_pcie_setup(blob, bd);
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
 #endif
 
 	return 0;
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index fb8525f..53fc4f8 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -12,7 +12,6 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/fsl_serdes.h>
 #include <asm/arch/ls102xa_stream_id.h>
-#include <asm/pcie_layerscape.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <fsl_ifc.h>
@@ -475,8 +474,8 @@ int ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
 
-#ifdef CONFIG_PCIE_LAYERSCAPE
-	ft_pcie_setup(blob, bd);
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
 #endif
 
 	return 0;
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index bcad8f2..1b0b814 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -11,7 +11,6 @@
 #include <asm/io.h>
 #include <errno.h>
 #include <malloc.h>
-#include <asm/pcie_layerscape.h>
 
 #ifndef CONFIG_SYS_PCI_MEMORY_BUS
 #define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
@@ -486,7 +485,7 @@ static void ft_pcie_ls_setup(void *blob, const char *pci_compat,
 		fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
 }
 
-void ft_pcie_setup(void *blob, bd_t *bd)
+void ft_pci_setup(void *blob, bd_t *bd)
 {
 	#ifdef CONFIG_PCIE1
 	ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE1_ADDR, PCIE1);
@@ -506,7 +505,7 @@ void ft_pcie_setup(void *blob, bd_t *bd)
 }
 
 #else
-void ft_pcie_setup(void *blob, bd_t *bd)
+void ft_pci_setup(void *blob, bd_t *bd)
 {
 }
 #endif
-- 
1.9.1

[U-Boot] [PATCH 2/2][v2] pci/layerscape: fix link and class issues to support ls2085a

[Minghuan Lian]

1. LS2085a provides PCIE_LUT_DBG register rather than PCIE_LDBG
   to show the link status, so the patch fixes it.
2. Increase the delay time to make sure that link training
   has finished.
3. Return invalid value when accessing multi-function device
4. For LS2085a DBI_RO_WR_EN bit is cleared as default, so we
   must set this bit before change DBI register value.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
---
change log:
v1-v2: no change

 drivers/pci/pcie_layerscape.c | 47 ++++++++++++++++++++++++++++++-------------
 1 file changed, 33 insertions(+), 14 deletions(-)

diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 1b0b814..402c519 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -49,11 +49,20 @@
 #define PCIE_ATU_FUNC(x)		(((x) & 0x7) << 16)
 #define PCIE_ATU_UPPER_TARGET		0x91C
 
+/* LUT registers */
+#define PCIE_LUT_BASE		0x80000
+#define PCIE_LUT_DBG		0x7FC
+
+#define PCIE_DBI_RO_WR_EN	0x8bc
+
 #define PCIE_LINK_CAP		0x7c
 #define PCIE_LINK_SPEED_MASK	0xf
 #define PCIE_LINK_STA		0x82
 
-#define PCIE_DBI_SIZE		(4 * 1024) /* 4K */
+#define LTSSM_STATE_MASK	0x3f
+#define LTSSM_PCIE_L0		0x11 /* L0 state */
+
+#define PCIE_DBI_SIZE		0x100000 /* 1M */
 
 struct ls_pcie {
 	int idx;
@@ -103,8 +112,6 @@ struct ls_pcie_info {
 
 /* PEX1/2 Misc Ports Status Register */
 #define LTSSM_STATE_SHIFT	20
-#define LTSSM_STATE_MASK	0x3f
-#define LTSSM_PCIE_L0		0x11 /* L0 state */
 
 static int ls_pcie_link_state(struct ls_pcie *pcie)
 {
@@ -121,18 +128,18 @@ static int ls_pcie_link_state(struct ls_pcie *pcie)
 	return 1;
 }
 #else
-#define PCIE_LDBG 0x7FC
-
 static int ls_pcie_link_state(struct ls_pcie *pcie)
 {
 	u32 state;
 
-	state = readl(pcie->dbi + PCIE_LDBG);
-	if (state)
-		return 1;
+	state = readl(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) &
+		LTSSM_STATE_MASK;
+	if (state < LTSSM_PCIE_L0) {
+		debug("....PCIe link error. LTSSM=0x%02x.\n", state);
+		return 0;
+	}
 
-	debug("....PCIe link error.\n");
-	return 0;
+	return 1;
 }
 #endif
 
@@ -148,7 +155,11 @@ static int ls_pcie_link_up(struct ls_pcie *pcie)
 	/* Try to download speed to gen1 */
 	cap = readl(pcie->dbi + PCIE_LINK_CAP);
 	writel((cap & (~PCIE_LINK_SPEED_MASK)) | 1, pcie->dbi + PCIE_LINK_CAP);
-	udelay(2000);
+	/*
+	 * Notice: the following delay has critical impact on link training
+	 * if too short (<30ms) the link doesn't get up.
+	 */
+	mdelay(100);
 	state = ls_pcie_link_state(pcie);
 	if (state)
 		return state;
@@ -250,6 +261,10 @@ static int ls_pcie_addr_valid(struct pci_controller *hose, pci_dev_t d)
 	if (PCI_DEV(d) > 0)
 		return -EINVAL;
 
+	/* Controller does not support multi-function in RC mode */
+	if ((PCI_BUS(d) == hose->first_busno) && (PCI_FUNC(d) > 0))
+		return -EINVAL;
+
 	return 0;
 }
 
@@ -326,8 +341,12 @@ static void ls_pcie_setup_ctrl(struct ls_pcie *pcie,
 	pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0);
 
 	/* program correct class for RC */
+	writel(1, pcie->dbi + PCIE_DBI_RO_WR_EN);
 	pci_hose_write_config_word(hose, dev, PCI_CLASS_DEVICE,
 				   PCI_CLASS_BRIDGE_PCI);
+#ifndef CONFIG_LS102XA
+	writel(0, pcie->dbi + PCIE_DBI_RO_WR_EN);
+#endif
 }
 
 int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info *info)
@@ -416,9 +435,9 @@ int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info *info)
 	}
 
 	/* Print the negotiated PCIe link width */
-	pci_hose_read_config_word(hose, dev, PCIE_LINK_STA, &temp16);
-		printf("x%d gen%d, regs @ 0x%lx\n", (temp16 & 0x3f0) >> 4,
-		       (temp16 & 0xf), info->regs);
+	pci_hose_read_config_word(hose, pdev, PCIE_LINK_STA, &temp16);
+	printf("x%d gen%d, regs @ 0x%lx\n", (temp16 & 0x3f0) >> 4,
+	       (temp16 & 0xf), info->regs);
 
 	if (ep_mode)
 		return busno;
-- 
1.9.1

[U-Boot] [PATCH 1/2][v2] pci/layerscape: remove unnecessary pcie_layerscape.h

[Tom Rini]

On Thu, Mar 12, 2015 at 10:58:48AM +0800, Minghuan Lian wrote:

> The patch uses the common function name ft_pci_setup to replace
> ft_pcie_setup, then removes unnecessary pcie_layerscape.h because
> all the functions have been declared in common.h.
> 
> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>

Thanks for reworking things!

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH 1/2][v2] pci/layerscape: remove unnecessary pcie_layerscape.h

[York Sun]

On 03/11/2015 07:58 PM, Minghuan Lian wrote:
> The patch uses the common function name ft_pci_setup to replace
> ft_pcie_setup, then removes unnecessary pcie_layerscape.h because
> all the functions have been declared in common.h.
> 
> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
> ---
> change log:
> v1-v2: remove unnecessary pcie_layerscape.h
> 

Applied to fsl-qoriq master, awaiting upstream.

York

[U-Boot] [PATCH 2/2][v2] pci/layerscape: fix link and class issues to support ls2085a

[York Sun]

On 03/11/2015 07:58 PM, Minghuan Lian wrote:
> 1. LS2085a provides PCIE_LUT_DBG register rather than PCIE_LDBG
>    to show the link status, so the patch fixes it.
> 2. Increase the delay time to make sure that link training
>    has finished.
> 3. Return invalid value when accessing multi-function device
> 4. For LS2085a DBI_RO_WR_EN bit is cleared as default, so we
>    must set this bit before change DBI register value.
> 
> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
> ---
> change log:
> v1-v2: no change
> 

Applied to fsl-qoriq master, awaiting upstream.

York