From mboxrd@z Thu Jan  1 00:00:00 1970
From: York Sun <yorksun@freescale.com>
Date: Thu, 23 Apr 2015 16:30:52 -0700
Subject: [U-Boot] [PATCH 2/2][v2] pci/layerscape: fix link and class
 issues to support ls2085a
In-Reply-To: <1426129129-10149-2-git-send-email-Minghuan.Lian@freescale.com>
References: <1426129129-10149-1-git-send-email-Minghuan.Lian@freescale.com>
 <1426129129-10149-2-git-send-email-Minghuan.Lian@freescale.com>
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On 03/11/2015 07:58 PM, Minghuan Lian wrote:
> 1. LS2085a provides PCIE_LUT_DBG register rather than PCIE_LDBG
>    to show the link status, so the patch fixes it.
> 2. Increase the delay time to make sure that link training
>    has finished.
> 3. Return invalid value when accessing multi-function device
> 4. For LS2085a DBI_RO_WR_EN bit is cleared as default, so we
>    must set this bit before change DBI register value.
> 
> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
> ---
> change log:
> v1-v2: no change
> 

Applied to fsl-qoriq master, awaiting upstream.

York