From mboxrd@z Thu Jan 1 00:00:00 1970 From: York Sun Date: Wed, 29 Apr 2015 08:04:30 -0700 Subject: [U-Boot] [PATCH v2] armv8: caches: Added routine to set non cacheable region In-Reply-To: <36afeeb6504576ba92012c597d24b81517b085c7.1430296529.git.michal.simek@xilinx.com> References: <36afeeb6504576ba92012c597d24b81517b085c7.1430296529.git.michal.simek@xilinx.com> Message-ID: <5540F2FE.30508@freescale.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 04/29/2015 01:35 AM, Michal Simek wrote: > Added routine mmu_set_region_dcache_behaviour() to set a > particular region as non cacheable. > > Define dummy routine for mmu_set_region_dcache_behaviour() > to handle incase of dcache off. > > Signed-off-by: Siva Durga Prasad Paladugu > Signed-off-by: Michal Simek > --- > > Changes in v2: > - Fix patch subject (remove addional zzz from v1) > - Remove armv8: caches: Disable dcache after flush patch from this > series based on the talk with Mark Rutland (patch is not needed > anymore) > > arch/arm/cpu/armv8/cache_v8.c | 23 +++++++++++++++++++++++ > arch/arm/include/asm/system.h | 28 ++++++++++++++++++---------- > 2 files changed, 41 insertions(+), 10 deletions(-) > > diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c > index c5ec5297cd39..25a2136a3cdf 100644 > --- a/arch/arm/cpu/armv8/cache_v8.c > +++ b/arch/arm/cpu/armv8/cache_v8.c > @@ -139,6 +139,24 @@ int dcache_status(void) > return (get_sctlr() & CR_C) != 0; > } > > +void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, > + enum dcache_option option) > +{ > + /* get the level2_table0 start address */ > + u64 *page_table = (u64 *)(gd->arch.tlb_addr + 0x3000); How is this table address defined? For our SoC (fsl-lsch3), we have multiple level 2 tables. Using fixed address doesn't seem right here. York