From mboxrd@z Thu Jan 1 00:00:00 1970 From: York Sun Date: Tue, 5 May 2015 09:30:19 -0700 Subject: [U-Boot] [PATCH v3] T2080QDS/PCIe: Soft Reset PCIe on T2080QDS for down-training issue In-Reply-To: <1427357589-42350-1-git-send-email-B45475@freescale.com> References: <1427357589-42350-1-git-send-email-B45475@freescale.com> Message-ID: <5548F01B.3090403@freescale.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 03/26/2015 01:13 AM, Zhao Qiang wrote: > T2080QDS PEX1/Slot#1 will down-train from x4 to x2, > with SRDS_PRTCL_S1 = 0x66 and SRDS_PRTCL_S2 = 0x15. > Soft reset PCIe can fix this issue. > > Signed-off-by: Zhao Qiang > --- > changes for v2 > - modify the commit message > changes for v3 > - use CONFIG_FSL_PCIE_RESET instead of CONFIG_FSL_PCIE_T2080QDS_RESET > Applied to u-boot-mpc85xx master. Awaiting upstream. York