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From: York Sun <yorksun@freescale.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] fsl/pci: Set CFG_READY for PCIe v3.0 and later
Date: Tue, 5 May 2015 09:32:14 -0700	[thread overview]
Message-ID: <5548F08E.3020309@freescale.com> (raw)
In-Reply-To: <1427433879-10121-1-git-send-email-Minghuan.Lian@freescale.com>



On 03/26/2015 10:24 PM, Minghuan Lian wrote:
> Freescale PCIe controllers v3.0 and later need to set bit
> CFG_READY to allow all inbound configuration transactions
> to be processed normally when in EP mode. However, bit
> CFG_READY has been moved from PCIe configuration space to
> CCSR PCIe configuration register comparing previous version.
> The patch is to set this bit according to PCIe version.
> 
> Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
> ---

Applied to u-boot-mpc85xx master. Awaiting upstream.

York

      reply	other threads:[~2015-05-05 16:32 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-03-27  5:24 [U-Boot] [PATCH] fsl/pci: Set CFG_READY for PCIe v3.0 and later Minghuan Lian
2015-05-05 16:32 ` York Sun [this message]

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