From mboxrd@z Thu Jan 1 00:00:00 1970 From: York Sun Date: Tue, 5 May 2015 09:32:14 -0700 Subject: [U-Boot] [PATCH] fsl/pci: Set CFG_READY for PCIe v3.0 and later In-Reply-To: <1427433879-10121-1-git-send-email-Minghuan.Lian@freescale.com> References: <1427433879-10121-1-git-send-email-Minghuan.Lian@freescale.com> Message-ID: <5548F08E.3020309@freescale.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 03/26/2015 10:24 PM, Minghuan Lian wrote: > Freescale PCIe controllers v3.0 and later need to set bit > CFG_READY to allow all inbound configuration transactions > to be processed normally when in EP mode. However, bit > CFG_READY has been moved from PCIe configuration space to > CCSR PCIe configuration register comparing previous version. > The patch is to set this bit according to PCIe version. > > Signed-off-by: Ed Swarthout > Signed-off-by: Roy Zang > Signed-off-by: Minghuan Lian > --- Applied to u-boot-mpc85xx master. Awaiting upstream. York