* [U-Boot] [PATCH] board/t2080rdb: reset CS4315 PHY
@ 2015-04-21 10:40 Shengzhou Liu
0 siblings, 0 replies; 3+ messages in thread
From: Shengzhou Liu @ 2015-04-21 10:40 UTC (permalink / raw)
To: u-boot
CS4315 PHY doesn't phy reset by software, it needs to
reset it by hardware reset via CPLD control.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
---
board/freescale/t208xrdb/cpld.h | 3 +++
board/freescale/t208xrdb/t208xrdb.c | 7 +++++++
2 files changed, 10 insertions(+)
diff --git a/board/freescale/t208xrdb/cpld.h b/board/freescale/t208xrdb/cpld.h
index 3f15338..9bd5247 100644
--- a/board/freescale/t208xrdb/cpld.h
+++ b/board/freescale/t208xrdb/cpld.h
@@ -40,3 +40,6 @@ void cpld_write(unsigned int reg, u8 value);
#define CPLD_LBMAP_RESET 0xFF
#define CPLD_LBMAP_SHIFT 0x03
#define CPLD_BOOT_SEL 0x80
+
+/* RSTCON Register */
+#define CPLD_RSTCON_EDC_RST 0x04
diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c
index ad393df..35c6efe 100644
--- a/board/freescale/t208xrdb/t208xrdb.c
+++ b/board/freescale/t208xrdb/t208xrdb.c
@@ -107,6 +107,13 @@ unsigned long get_board_ddr_clk(void)
int misc_init_r(void)
{
+ int reg;
+
+ /* Reset CS4315 PHY */
+ reg = CPLD_READ(reset_ctl);
+ reg |= CPLD_RSTCON_EDC_RST;
+ CPLD_WRITE(reset_ctl, reg);
+
return 0;
}
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [U-Boot] [PATCH] board/t2080rdb: reset cs4315 phy
@ 2015-04-22 2:59 Shengzhou Liu
2015-05-05 16:37 ` York Sun
0 siblings, 1 reply; 3+ messages in thread
From: Shengzhou Liu @ 2015-04-22 2:59 UTC (permalink / raw)
To: u-boot
CS4315 PHY doesn't support phy-reset by software, it
needs to reset it by hardware via CPLD control.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
---
board/freescale/t208xrdb/cpld.h | 3 +++
board/freescale/t208xrdb/t208xrdb.c | 7 +++++++
2 files changed, 10 insertions(+)
diff --git a/board/freescale/t208xrdb/cpld.h b/board/freescale/t208xrdb/cpld.h
index 3f15338..9bd5247 100644
--- a/board/freescale/t208xrdb/cpld.h
+++ b/board/freescale/t208xrdb/cpld.h
@@ -40,3 +40,6 @@ void cpld_write(unsigned int reg, u8 value);
#define CPLD_LBMAP_RESET 0xFF
#define CPLD_LBMAP_SHIFT 0x03
#define CPLD_BOOT_SEL 0x80
+
+/* RSTCON Register */
+#define CPLD_RSTCON_EDC_RST 0x04
diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c
index ad393df..0c2c1c5 100644
--- a/board/freescale/t208xrdb/t208xrdb.c
+++ b/board/freescale/t208xrdb/t208xrdb.c
@@ -107,6 +107,13 @@ unsigned long get_board_ddr_clk(void)
int misc_init_r(void)
{
+ u8 reg;
+
+ /* Reset CS4315 PHY */
+ reg = CPLD_READ(reset_ctl);
+ reg |= CPLD_RSTCON_EDC_RST;
+ CPLD_WRITE(reset_ctl, reg);
+
return 0;
}
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [U-Boot] [PATCH] board/t2080rdb: reset cs4315 phy
2015-04-22 2:59 [U-Boot] [PATCH] board/t2080rdb: reset cs4315 phy Shengzhou Liu
@ 2015-05-05 16:37 ` York Sun
0 siblings, 0 replies; 3+ messages in thread
From: York Sun @ 2015-05-05 16:37 UTC (permalink / raw)
To: u-boot
On 04/21/2015 07:59 PM, Shengzhou Liu wrote:
> CS4315 PHY doesn't support phy-reset by software, it
> needs to reset it by hardware via CPLD control.
>
> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
> ---
> board/freescale/t208xrdb/cpld.h | 3 +++
> board/freescale/t208xrdb/t208xrdb.c | 7 +++++++
> 2 files changed, 10 insertions(+)
>
Applied to u-boot-mpc85xx master. Awaiting upstream.
York
^ permalink raw reply [flat|nested] 3+ messages in thread
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