From: "Benoît Thébaudeau" <benoit.thebaudeau@advansee.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 1/6] imx: mx6q DDR3 init: Fix tMRD
Date: Fri, 1 Feb 2013 00:25:47 +0100 (CET) [thread overview]
Message-ID: <556140571.236438.1359674747008.JavaMail.root@advansee.com> (raw)
In-Reply-To: <510AFAED.3060702@boundarydevices.com>
Hi Eric,
On Friday, February 1, 2013 12:14:53 AM, Eric Nelson wrote:
> On 01/30/2013 02:19 PM, Beno?t Th?baudeau wrote:
> > MMDC1_MDCFG1.tMRD should be set to max(tMRD, tMOD) for DDR3.
> >
> > For all DDR3 speed bins:
> > tMRD(min) = 4 nCK
> > tMOD(min) = max(12 nCK, 15 ns)
> >
> > Hence, MMDC1_MDCFG1.tMRD should be set to max(12 nCK, 15 ns), which is 12
> > nCK
> > at 532 MHz, encoded as 0xB in the bit-field MMDC1_MDCFG1[8:5].
> >
> > Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> > ---
> > board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
> > b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
> > index c86cd40..9ac8027 100644
> > --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
> > +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
> > @@ -110,7 +110,7 @@ DATA 4 0x021b0018 0x00081740
> >
> > DATA 4 0x021b001c 0x00008000
> > DATA 4 0x021b000c 0x555A7975
> > -DATA 4 0x021b0010 0xFF538E64
> > +DATA 4 0x021b0010 0xFF538F64
> > DATA 4 0x021b0014 0x01FF00DB
> > DATA 4 0x021b002c 0x000026D2
> >
> >
>
> Hi Beno?t,
>
> I've been able to confirm operation of this complete patch set
> on a SABRE Lite here, but only that (boots normally).
Great.
> I'll try to scare up a board we can place on an extended burn-in.
That'd be good.
> What prompted you to walk the list? Was there a specific failure
> that this addressed?
No specific failure. The only issue that I get from time to time is errors in
the Linux SD driver, but this is probably unrelated.
The only reason was that I was looking for possible better performance on the
RAM side because I am working on very intensive RAM accessing applications. So I
checked the init code to see if it was optimal, and I found these issues besides
the small possible performance gain.
So far, the default mtest passed on my board. The alternate mtest and more Linux
stress tests might be interesting too.
Best regards,
Beno?t
next prev parent reply other threads:[~2013-01-31 23:25 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-01-30 21:19 [U-Boot] [PATCH 1/6] imx: mx6q DDR3 init: Fix tMRD Benoît Thébaudeau
2013-01-30 21:19 ` [U-Boot] [PATCH 2/6] imx: mx6q DDR3 init: Fix tXPR Benoît Thébaudeau
2013-01-30 21:19 ` [U-Boot] [PATCH 3/6] imx: mx6q DDR3 init: Fix SDE_to_RST Benoît Thébaudeau
2013-01-30 21:19 ` [U-Boot] [PATCH 4/6] imx: mx6q DDR3 init: Fix RST_to_CKE Benoît Thébaudeau
2013-01-30 21:19 ` [U-Boot] [PATCH 5/6] imx: mx6q DDR3 init: Fix MR0.PPD Benoît Thébaudeau
2013-01-30 21:19 ` [U-Boot] [PATCH 6/6] imx: mx6q DDR3 init: Benefit from available CL = 7 Benoît Thébaudeau
2013-01-31 23:14 ` [U-Boot] [PATCH 1/6] imx: mx6q DDR3 init: Fix tMRD Eric Nelson
2013-01-31 23:25 ` Benoît Thébaudeau [this message]
2013-02-01 18:28 ` Eric Nelson
2013-02-01 18:29 ` Benoît Thébaudeau
2013-02-12 12:53 ` Stefano Babic
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