From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefano Babic Date: Tue, 26 May 2015 14:16:20 +0200 Subject: [U-Boot] [PATCH] imx: dma: correct MXS_DMA_ALIGNMENT In-Reply-To: <1432088928-7414-1-git-send-email-Peng.Fan@freescale.com> References: <1432088928-7414-1-git-send-email-Peng.Fan@freescale.com> Message-ID: <55646414.2000706@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 20/05/2015 04:28, Peng Fan wrote: > We should not hardcode MXS_DMA_ALIGNMENT to 32, since we can not guarantee > that socs' cache line size is 32 bytes. > If on chips whose cache line size is 64 bytes, error occurs: > " > NAND: ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0 > ERROR: v7_dcache_inval_range - stop address is not aligned - 0xbdf1f4a0 > ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0 > " > Align MXS_DMA_ALIGNMENT with ARCH_DMA_MINALIGN whose value is same to > CONFIG_SYS_CACHELINE_SIZE if CONFIG_SYS_CACHELINE_SIZE defined. > > Signed-off-by: Peng Fan > --- > arch/arm/include/asm/imx-common/dma.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm/include/asm/imx-common/dma.h b/arch/arm/include/asm/imx-common/dma.h > index d5c1f7f..7d421b3 100644 > --- a/arch/arm/include/asm/imx-common/dma.h > +++ b/arch/arm/include/asm/imx-common/dma.h > @@ -22,7 +22,7 @@ > #define DMA_PIO_WORDS CONFIG_ARCH_DMA_PIO_WORDS > #endif > > -#define MXS_DMA_ALIGNMENT 32 > +#define MXS_DMA_ALIGNMENT ARCH_DMA_MINALIGN > > /* > * MXS DMA channels > Applied to u-boot-imx, thanks! Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de =====================================================================