[U-Boot] [PATCH 01/20] armv8/ls2085ardb: Add eth & phy f/w loading support

[U-Boot] [PATCH 01/20] armv8/ls2085ardb: Add eth & phy f/w loading support

[Prabhakar Kushwaha]

Add support for board eth initialization and support for loading phy
firmware. PHY firmware needs to be loaded from board_eth_init() because
all the MACs are not initialized by ldpaa_eth driver.

Signed-off-by: pankaj chauhan <pankaj.chauhan@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
 board/freescale/ls2085ardb/Makefile        |   2 +-
 board/freescale/ls2085ardb/eth_ls2085rdb.c | 133 +++++++++++++++++++++++++++++
 board/freescale/ls2085ardb/ls2085ardb.c    |  13 ---
 include/configs/ls2085ardb.h               |  23 +++++
 4 files changed, 157 insertions(+), 14 deletions(-)
 create mode 100644 board/freescale/ls2085ardb/eth_ls2085rdb.c

diff --git a/board/freescale/ls2085ardb/Makefile b/board/freescale/ls2085ardb/Makefile
index 0bfe21c..de383cc 100644
--- a/board/freescale/ls2085ardb/Makefile
+++ b/board/freescale/ls2085ardb/Makefile
@@ -4,5 +4,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y += ls2085ardb.o
+obj-y += ls2085ardb.o eth_ls2085rdb.o
 obj-y += ddr.o
diff --git a/board/freescale/ls2085ardb/eth_ls2085rdb.c b/board/freescale/ls2085ardb/eth_ls2085rdb.c
new file mode 100644
index 0000000..60af079
--- /dev/null
+++ b/board/freescale/ls2085ardb/eth_ls2085rdb.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <malloc.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <fm_eth.h>
+#include <asm/io.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch-fsl-lsch3/immap_lsch3.h>
+#include <fsl-mc/ldpaa_wriop.h>
+
+int load_firmware_cortina(struct phy_device *phy_dev)
+{
+	if (phy_dev->drv->config)
+		return phy_dev->drv->config(phy_dev);
+
+	return 0;
+}
+
+void load_phy_firmware(void)
+{
+	int i;
+	u8 phy_addr;
+	struct phy_device *phy_dev;
+	struct mii_dev *dev;
+	phy_interface_t interface;
+
+	/*Initialize and upload firmware for all the PHYs*/
+	for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC8; i++) {
+		interface = wriop_get_enet_if(i);
+		if (interface == PHY_INTERFACE_MODE_XGMII) {
+			dev = wriop_get_mdio(i);
+			phy_addr = wriop_get_phy_address(i);
+			phy_dev = phy_find_by_mask(dev, 1 << phy_addr,
+						interface);
+			if (!phy_dev) {
+				printf("No phydev for phyaddr %d\n", phy_addr);
+				continue;
+			}
+
+			/*Flash firmware for All CS4340 PHYS */
+			if (phy_dev->phy_id == PHY_UID_CS4340)
+				load_firmware_cortina(phy_dev);
+		}
+	}
+}
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_FSL_MC_ENET)
+	int i, interface;
+	struct memac_mdio_info mdio_info;
+	struct mii_dev *dev;
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 srds_s1;
+	struct memac_mdio_controller *reg;
+
+	srds_s1 = in_le32(&gur->rcwsr[28]) &
+				FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
+	srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+
+	reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
+	mdio_info.regs = reg;
+	mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
+
+	/* Register the EMI 1 */
+	fm_memac_mdio_init(bis, &mdio_info);
+
+	reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
+	mdio_info.regs = reg;
+	mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
+
+	/* Register the EMI 2 */
+	fm_memac_mdio_init(bis, &mdio_info);
+
+	switch (srds_s1) {
+	case 0x2A:
+		wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1);
+		wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2);
+		wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3);
+		wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4);
+		wriop_set_phy_address(WRIOP1_DPMAC5, AQ_PHY_ADDR1);
+		wriop_set_phy_address(WRIOP1_DPMAC6, AQ_PHY_ADDR2);
+		wriop_set_phy_address(WRIOP1_DPMAC7, AQ_PHY_ADDR3);
+		wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4);
+
+		break;
+	default:
+		printf("SerDes1 protocol 0x%x is not supported on LS2085aRDB\n",
+		       srds_s1);
+		break;
+	}
+
+	for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC4; i++) {
+		interface = wriop_get_enet_if(i);
+		switch (interface) {
+		case PHY_INTERFACE_MODE_XGMII:
+			dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
+			wriop_set_mdio(i, dev);
+			break;
+		default:
+			break;
+		}
+	}
+
+	for (i = WRIOP1_DPMAC5; i <= WRIOP1_DPMAC8; i++) {
+		switch (wriop_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_XGMII:
+			dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
+			wriop_set_mdio(i, dev);
+			break;
+		default:
+			break;
+		}
+	}
+
+	/* Load CORTINA CS4340 PHY firmware */
+	load_phy_firmware();
+
+	cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+	return pci_eth_init(bis);
+}
diff --git a/board/freescale/ls2085ardb/ls2085ardb.c b/board/freescale/ls2085ardb/ls2085ardb.c
index d05f2bc..6cb7b13 100644
--- a/board/freescale/ls2085ardb/ls2085ardb.c
+++ b/board/freescale/ls2085ardb/ls2085ardb.c
@@ -176,19 +176,6 @@ unsigned long get_dram_size_to_hide(void)
 	return dram_to_hide;
 }
 
-int board_eth_init(bd_t *bis)
-{
-	int error = 0;
-
-#ifdef CONFIG_FSL_MC_ENET
-	error = cpu_eth_init(bis);
-#endif
-
-	error = pci_eth_init(bis);
-
-	return error;
-}
-
 #ifdef CONFIG_FSL_MC_ENET
 void fdt_fixup_board_enet(void *fdt)
 {
diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h
index d1c2548..62f13f9 100644
--- a/include/configs/ls2085ardb.h
+++ b/include/configs/ls2085ardb.h
@@ -302,4 +302,27 @@ unsigned long get_board_sys_clk(void);
 	"kernel_load=0xa0000000\0"		\
 	"kernel_size=0x1000000\0"
 
+/* MAC/PHY configuration */
+#ifdef CONFIG_FSL_MC_ENET
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_CORTINA
+#define CONFIG_PHYLIB
+#define	CONFIG_SYS_CORTINA_FW_IN_NOR
+#define CONFIG_CORTINA_FW_ADDR		0x581000000
+#define CONFIG_CORTINA_FW_LENGTH	0x40000
+
+#define CORTINA_PHY_ADDR1	0x10
+#define CORTINA_PHY_ADDR2	0x11
+#define CORTINA_PHY_ADDR3	0x12
+#define CORTINA_PHY_ADDR4	0x13
+#define AQ_PHY_ADDR1		0x00
+#define AQ_PHY_ADDR2		0x01
+#define AQ_PHY_ADDR3		0x02
+#define AQ_PHY_ADDR4		0x03
+
+#define CONFIG_MII
+#define CONFIG_ETHPRIME		"DPNI1"
+#define CONFIG_PHY_GIGE
+#endif
+
 #endif /* __LS2_RDB_H */
-- 
1.9.1

[U-Boot] [PATCH 02/20] armv8/ls2085ardb: add hwconfig setting for eSDHC

[Prabhakar Kushwaha]

From: Yangbo Lu <yangbo.lu@freescale.com>

Add hwconfig setting for eSDHC since it shares some pins with other
IP block.

Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
 board/freescale/ls2085ardb/ls2085ardb.c | 36 +++++++++++++++++++++++++++++++++
 include/configs/ls2085ardb.h            |  2 ++
 2 files changed, 38 insertions(+)

diff --git a/board/freescale/ls2085ardb/ls2085ardb.c b/board/freescale/ls2085ardb/ls2085ardb.c
index 6cb7b13..e0a8a41 100644
--- a/board/freescale/ls2085ardb/ls2085ardb.c
+++ b/board/freescale/ls2085ardb/ls2085ardb.c
@@ -10,6 +10,7 @@
 #include <fsl_ifc.h>
 #include <fsl_ddr.h>
 #include <asm/io.h>
+#include <hwconfig.h>
 #include <fdt_support.h>
 #include <libfdt.h>
 #include <fsl_debug_server.h>
@@ -21,8 +22,15 @@
 #include "../common/qixis.h"
 #include "ls2085ardb_qixis.h"
 
+#define PIN_MUX_SEL_SDHC	0x00
+
+#define SET_SDHC_MUX_SEL(reg, value)	((reg & 0xf0) | value)
 DECLARE_GLOBAL_DATA_PTR;
 
+enum {
+	MUX_TYPE_SDHC,
+};
+
 unsigned long long get_qixis_addr(void)
 {
 	unsigned long long addr;
@@ -129,6 +137,34 @@ int board_early_init_f(void)
 	return 0;
 }
 
+int config_board_mux(int ctrl_type)
+{
+	u8 reg5;
+
+	reg5 = QIXIS_READ(brdcfg[5]);
+
+	switch (ctrl_type) {
+	case MUX_TYPE_SDHC:
+		reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
+		break;
+	default:
+		printf("Wrong mux interface type\n");
+		return -1;
+	}
+
+	QIXIS_WRITE(brdcfg[5], reg5);
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	if (hwconfig("sdhc"))
+		config_board_mux(MUX_TYPE_SDHC);
+
+	return 0;
+}
+
 void detail_board_ddr_info(void)
 {
 	puts("\nDDR    ");
diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h
index 62f13f9..29c934e 100644
--- a/include/configs/ls2085ardb.h
+++ b/include/configs/ls2085ardb.h
@@ -288,6 +288,8 @@ unsigned long get_board_sys_clk(void);
 #define CONFIG_DOS_PARTITION
 #endif
 
+#define CONFIG_MISC_INIT_R
+
 /* Initial environment variables */
 #undef CONFIG_EXTRA_ENV_SETTINGS
 #define CONFIG_EXTRA_ENV_SETTINGS		\
-- 
1.9.1

[U-Boot] [PATCH 03/20] armv8/ls2085a: Enable Date command for QDS and RDB

[Prabhakar Kushwaha]

From: Priyanka Jain <Priyanka.Jain@freescale.com>

Enable Date command for QDS and RDB boards

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
 include/configs/ls2085aqds.h | 1 +
 include/configs/ls2085ardb.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/include/configs/ls2085aqds.h b/include/configs/ls2085aqds.h
index 711d529..87e9333 100644
--- a/include/configs/ls2085aqds.h
+++ b/include/configs/ls2085aqds.h
@@ -288,6 +288,7 @@ unsigned long get_board_ddr_clk(void);
 #define RTC
 #define CONFIG_RTC_DS3231               1
 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
+#define CONFIG_CMD_DATE
 
 /* EEPROM */
 #define CONFIG_ID_EEPROM
diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h
index 29c934e..ad618a8 100644
--- a/include/configs/ls2085ardb.h
+++ b/include/configs/ls2085ardb.h
@@ -253,6 +253,7 @@ unsigned long get_board_sys_clk(void);
 #define RTC
 #define CONFIG_RTC_DS3231               1
 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
+#define CONFIG_CMD_DATE
 
 /* EEPROM */
 #define CONFIG_ID_EEPROM
-- 
1.9.1

[U-Boot] [PATCH 04/20] armv8/ls2085aqds: Add support of 0x49 in ethernet

[Prabhakar Kushwaha]

Add support of 0x49 SerDes protocol for ls2085aqds platform

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
 board/freescale/ls2085aqds/eth.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/board/freescale/ls2085aqds/eth.c b/board/freescale/ls2085aqds/eth.c
index 5ba4770..f32ace2 100644
--- a/board/freescale/ls2085aqds/eth.c
+++ b/board/freescale/ls2085aqds/eth.c
@@ -210,6 +210,7 @@ static void initialize_dpmac_to_slot(void)
 	switch (serdes2_prtcl) {
 	case 0x07:
 	case 0x08:
+	case 0x49:
 		printf("qds: WRIOP: Supported SerDes Protocol 0x%02x\n",
 		       serdes2_prtcl);
 		lane_to_slot_fsm2[0] = EMI1_SLOT4;
@@ -247,6 +248,7 @@ void ls2085a_handle_phy_interface_sgmii(int dpmac_id)
 	switch (serdes2_prtcl) {
 	case 0x07:
 	case 0x08:
+	case 0x49:
 		lane = serdes_get_first_lane(FSL_SRDS_2, SGMII9 +
 							(dpmac_id - 9));
 		slot = lane_to_slot_fsm2[lane];
-- 
1.9.1

[U-Boot] [PATCH 05/20] armv8/ls2085a: call ft_pcie_setup() to change dts status

[Prabhakar Kushwaha]

From: Minghuan Lian <Minghuan.Lian@freescale.com>

 1. The patch call ft_pcie_setup() to disable PCIe dts node if
    corresponding PCIe controller is disabled according to RCW.
 2. Fix LS2085a PCIe compatible

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
 board/freescale/ls2085a/ls2085a.c       | 4 ++++
 board/freescale/ls2085aqds/ls2085aqds.c | 4 ++++
 board/freescale/ls2085ardb/ls2085ardb.c | 4 ++++
 include/configs/ls2085a_common.h        | 3 ++-
 4 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/board/freescale/ls2085a/ls2085a.c b/board/freescale/ls2085a/ls2085a.c
index dd0acf2..afb99d1 100644
--- a/board/freescale/ls2085a/ls2085a.c
+++ b/board/freescale/ls2085a/ls2085a.c
@@ -142,6 +142,10 @@ int ft_board_setup(void *blob, bd_t *bd)
 	fsl_mc_ldpaa_exit(bd);
 #endif
 
+#ifdef CONFIG_PCI
+	ft_pcie_setup(blob, bd);
+#endif
+
 	return 0;
 }
 #endif
diff --git a/board/freescale/ls2085aqds/ls2085aqds.c b/board/freescale/ls2085aqds/ls2085aqds.c
index 6a22122..b103224 100644
--- a/board/freescale/ls2085aqds/ls2085aqds.c
+++ b/board/freescale/ls2085aqds/ls2085aqds.c
@@ -255,6 +255,10 @@ int ft_board_setup(void *blob, bd_t *bd)
 	fsl_mc_ldpaa_exit(bd);
 #endif
 
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+
 	return 0;
 }
 #endif
diff --git a/board/freescale/ls2085ardb/ls2085ardb.c b/board/freescale/ls2085ardb/ls2085ardb.c
index e0a8a41..5abf273 100644
--- a/board/freescale/ls2085ardb/ls2085ardb.c
+++ b/board/freescale/ls2085ardb/ls2085ardb.c
@@ -253,6 +253,10 @@ int ft_board_setup(void *blob, bd_t *bd)
 	fsl_mc_ldpaa_exit(bd);
 #endif
 
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+
 	return 0;
 }
 #endif
diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h
index e270fc8..749c58d 100644
--- a/include/configs/ls2085a_common.h
+++ b/include/configs/ls2085a_common.h
@@ -186,7 +186,8 @@ unsigned long long get_qixis_addr(void);
 #define CONFIG_PCIE2		/* PCIE controler 2 */
 #define CONFIG_PCIE3		/* PCIE controler 3 */
 #define CONFIG_PCIE4		/* PCIE controler 4 */
-#define FSL_PCIE_COMPAT "fsl,20851a-pcie"
+#define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */
+#define FSL_PCIE_COMPAT "fsl,ls2085a-pcie"
 
 #define CONFIG_SYS_PCI_64BIT
 
-- 
1.9.1

[U-Boot] [PATCH 06/20] armv8/ls2085qds: Update SFP TX bit as "0" to enable XFI

[Prabhakar Kushwaha]

FPGA BRDCFG9[SFP_TX] should be clear in order to enable XFI ports.

Signed-off-by: Dai Haruki <Dai.Haruki@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
 board/freescale/ls2085aqds/eth.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/freescale/ls2085aqds/eth.c b/board/freescale/ls2085aqds/eth.c
index f32ace2..1f8a31f 100644
--- a/board/freescale/ls2085aqds/eth.c
+++ b/board/freescale/ls2085aqds/eth.c
@@ -53,7 +53,7 @@ static int riser_phy_addr[] = {
 #define EMI1_SLOT5	4
 #define EMI1_SLOT6	5
 #define EMI2		6
-#define SFP_TX		1
+#define SFP_TX		0
 
 static const char * const mdio_names[] = {
 	"LS2085A_QDS_MDIO0",
-- 
1.9.1

[U-Boot] [PATCH 07/20] armv8/ls2085rdb: Update PCA9547PW slave address

[Prabhakar Kushwaha]

Primary Mux on I2C1 controller has slave address as 0x75.
So update it's address.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
 include/configs/ls2085ardb.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h
index ad618a8..dab03bc 100644
--- a/include/configs/ls2085ardb.h
+++ b/include/configs/ls2085ardb.h
@@ -241,8 +241,8 @@ unsigned long get_board_sys_clk(void);
 /*
  * I2C
  */
-#define I2C_MUX_PCA_ADDR		0x77
-#define I2C_MUX_PCA_ADDR_PRI		0x77 /* Primary Mux*/
+#define I2C_MUX_PCA_ADDR		0x75
+#define I2C_MUX_PCA_ADDR_PRI		0x75 /* Primary Mux*/
 
 /* I2C bus multiplexer */
 #define I2C_MUX_CH_DEFAULT      0x8
-- 
1.9.1

[U-Boot] [PATCH 04/20] armv8/ls2085aqds: Add support of 0x49 in ethernet

[York Sun]

Prabhakar,


On 05/18/2015 12:08 AM, Prabhakar Kushwaha wrote:
> Add support of 0x49 SerDes protocol for ls2085aqds platform
> 

I would change the subject to "Add support of SerDes protocol 0x49". If you
want, you can put in commit message to explain what 0x49 does. Unless one is
familiar with SerDes protocols, it wouldn't be easy to link 0x49 to Ethernet.

York

> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> ---
>  board/freescale/ls2085aqds/eth.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/board/freescale/ls2085aqds/eth.c b/board/freescale/ls2085aqds/eth.c
> index 5ba4770..f32ace2 100644
> --- a/board/freescale/ls2085aqds/eth.c
> +++ b/board/freescale/ls2085aqds/eth.c
> @@ -210,6 +210,7 @@ static void initialize_dpmac_to_slot(void)
>  	switch (serdes2_prtcl) {
>  	case 0x07:
>  	case 0x08:
> +	case 0x49:
>  		printf("qds: WRIOP: Supported SerDes Protocol 0x%02x\n",
>  		       serdes2_prtcl);
>  		lane_to_slot_fsm2[0] = EMI1_SLOT4;
> @@ -247,6 +248,7 @@ void ls2085a_handle_phy_interface_sgmii(int dpmac_id)
>  	switch (serdes2_prtcl) {
>  	case 0x07:
>  	case 0x08:
> +	case 0x49:
>  		lane = serdes_get_first_lane(FSL_SRDS_2, SGMII9 +
>  							(dpmac_id - 9));
>  		slot = lane_to_slot_fsm2[lane];
> 

[U-Boot] [PATCH 05/20] armv8/ls2085a: call ft_pcie_setup() to change dts status

[York Sun]

Prabhakar and Minghuan,

On 05/18/2015 12:08 AM, Prabhakar Kushwaha wrote:
> From: Minghuan Lian <Minghuan.Lian@freescale.com>
> 
>  1. The patch call ft_pcie_setup() to disable PCIe dts node if
>     corresponding PCIe controller is disabled according to RCW.
>  2. Fix LS2085a PCIe compatible
> 
> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> ---
>  board/freescale/ls2085a/ls2085a.c       | 4 ++++
>  board/freescale/ls2085aqds/ls2085aqds.c | 4 ++++
>  board/freescale/ls2085ardb/ls2085ardb.c | 4 ++++
>  include/configs/ls2085a_common.h        | 3 ++-
>  4 files changed, 14 insertions(+), 1 deletion(-)
> 
> diff --git a/board/freescale/ls2085a/ls2085a.c b/board/freescale/ls2085a/ls2085a.c
> index dd0acf2..afb99d1 100644
> --- a/board/freescale/ls2085a/ls2085a.c
> +++ b/board/freescale/ls2085a/ls2085a.c
> @@ -142,6 +142,10 @@ int ft_board_setup(void *blob, bd_t *bd)
>  	fsl_mc_ldpaa_exit(bd);
>  #endif
>  
> +#ifdef CONFIG_PCI
> +	ft_pcie_setup(blob, bd);
> +#endif
> +

Shouldn't this function be called from SoC function? It is not a board-dependent
setup, but rather depending on RCW which is an SoC feature.

York

[U-Boot] [PATCH 07/20] armv8/ls2085rdb: Update PCA9547PW slave address

[York Sun]

On 05/18/2015 12:08 AM, Prabhakar Kushwaha wrote:
> Primary Mux on I2C1 controller has slave address as 0x75.
> So update it's address.

s/it's/its

York

[U-Boot] [PATCH 05/20] armv8/ls2085a: call ft_pcie_setup() to change dts status

[Lian M.H.]

Hi York,

1. board/freescale/ls2085a/ls2085a.c is for board ls2085a_emu like ls2085aqds.c not SoC file.
But I am not sure whether  emulator board should call this function.
2. ft_pcie_setup(blob, bd) should be changed to ft_pci_setup(blob, bd)
ft_pci_setup is the common function name defined in common.h

Thanks,
Minghuan

> -----Original Message-----
> From: Sun York-R58495
> Sent: Tuesday, May 26, 2015 11:54 PM
> To: Kushwaha Prabhakar-B32579; u-boot at lists.denx.de
> Cc: Lian Minghuan-B31939
> Subject: Re: [PATCH 05/20] armv8/ls2085a: call ft_pcie_setup() to change dts
> status
> 
> Prabhakar and Minghuan,
> 
> On 05/18/2015 12:08 AM, Prabhakar Kushwaha wrote:
> > From: Minghuan Lian <Minghuan.Lian@freescale.com>
> >
> >  1. The patch call ft_pcie_setup() to disable PCIe dts node if
> >     corresponding PCIe controller is disabled according to RCW.
> >  2. Fix LS2085a PCIe compatible
> >
> > Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
> > Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> > ---
> >  board/freescale/ls2085a/ls2085a.c       | 4 ++++
> >  board/freescale/ls2085aqds/ls2085aqds.c | 4 ++++
> > board/freescale/ls2085ardb/ls2085ardb.c | 4 ++++
> >  include/configs/ls2085a_common.h        | 3 ++-
> >  4 files changed, 14 insertions(+), 1 deletion(-)
> >
> > diff --git a/board/freescale/ls2085a/ls2085a.c
> > b/board/freescale/ls2085a/ls2085a.c
> > index dd0acf2..afb99d1 100644
> > --- a/board/freescale/ls2085a/ls2085a.c
> > +++ b/board/freescale/ls2085a/ls2085a.c
> > @@ -142,6 +142,10 @@ int ft_board_setup(void *blob, bd_t *bd)
> >  	fsl_mc_ldpaa_exit(bd);
> >  #endif
> >
> > +#ifdef CONFIG_PCI
> > +	ft_pcie_setup(blob, bd);
> > +#endif
> > +
> 
> Shouldn't this function be called from SoC function? It is not a board-
> dependent setup, but rather depending on RCW which is an SoC feature.
> 
> York

[U-Boot] [PATCH 05/20] armv8/ls2085a: call ft_pcie_setup() to change dts status

[Kushwaha Prabhakar]

> -----Original Message-----
> From: Lian Minghuan-B31939
> Sent: Wednesday, May 27, 2015 9:11 AM
> To: Sun York-R58495; Kushwaha Prabhakar-B32579; u-boot at lists.denx.de
> Subject: RE: [PATCH 05/20] armv8/ls2085a: call ft_pcie_setup() to change dts
> status
> 
> Hi York,
> 
> 1. board/freescale/ls2085a/ls2085a.c is for board ls2085a_emu like
> ls2085aqds.c not SoC file.
> But I am not sure whether  emulator board should call this function.
> 2. ft_pcie_setup(blob, bd) should be changed to ft_pci_setup(blob, bd)
> ft_pci_setup is the common function name defined in common.h



> 
> Thanks,
> Minghuan
> 
> > -----Original Message-----
> > From: Sun York-R58495
> > Sent: Tuesday, May 26, 2015 11:54 PM
> > To: Kushwaha Prabhakar-B32579; u-boot at lists.denx.de
> > Cc: Lian Minghuan-B31939
> > Subject: Re: [PATCH 05/20] armv8/ls2085a: call ft_pcie_setup() to
> > change dts status
> >
> > Prabhakar and Minghuan,
> >
> > On 05/18/2015 12:08 AM, Prabhakar Kushwaha wrote:
> > > From: Minghuan Lian <Minghuan.Lian@freescale.com>
> > >
> > >  1. The patch call ft_pcie_setup() to disable PCIe dts node if
> > >     corresponding PCIe controller is disabled according to RCW.
> > >  2. Fix LS2085a PCIe compatible
> > >
> > > Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
> > > Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> > > ---
> > >  board/freescale/ls2085a/ls2085a.c       | 4 ++++
> > >  board/freescale/ls2085aqds/ls2085aqds.c | 4 ++++
> > > board/freescale/ls2085ardb/ls2085ardb.c | 4 ++++
> > >  include/configs/ls2085a_common.h        | 3 ++-
> > >  4 files changed, 14 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/board/freescale/ls2085a/ls2085a.c
> > > b/board/freescale/ls2085a/ls2085a.c
> > > index dd0acf2..afb99d1 100644
> > > --- a/board/freescale/ls2085a/ls2085a.c
> > > +++ b/board/freescale/ls2085a/ls2085a.c
> > > @@ -142,6 +142,10 @@ int ft_board_setup(void *blob, bd_t *bd)
> > >  	fsl_mc_ldpaa_exit(bd);
> > >  #endif
> > >
> > > +#ifdef CONFIG_PCI
> > > +	ft_pcie_setup(blob, bd);
> > > +#endif
> > > +
> >
> > Shouldn't this function be called from SoC function? It is not a
> > board- dependent setup, but rather depending on RCW which is an SoC
> feature.
> >

There are 2 function and their relationship is like this
ft_pci_setup calling ft_pcie_ls_setup.

ft_pcie_ls_setup  is doing thing related to SoC.   
So I believe ft_pci_setup can be called from board file.  Not sure

--prabhakar

[U-Boot] [PATCH 05/20] armv8/ls2085a: call ft_pcie_setup() to change dts status

[York Sun]

On 05/26/2015 09:30 PM, Kushwaha Prabhakar-B32579 wrote:
>>>
>>> Shouldn't this function be called from SoC function? It is not a
>>> board- dependent setup, but rather depending on RCW which is an SoC
>> feature.
>>>
> 
> There are 2 function and their relationship is like this
> ft_pci_setup calling ft_pcie_ls_setup.
> 
> ft_pcie_ls_setup  is doing thing related to SoC.   
> So I believe ft_pci_setup can be called from board file.  Not sure
> 

I was thinking to move the call to fdt.c for the SoC, for example in the
function of ft_cpu_setup().

York