* [U-Boot] [PATCH 2/4] zynqmp: gem: Flush the rx buffers while transmitting
2015-05-26 11:40 [U-Boot] [PATCH 1/4] zynqmp: gem: Set data bus with to 64bit for arm64 Michal Simek
@ 2015-05-26 11:40 ` Michal Simek
2015-05-26 11:40 ` [U-Boot] [PATCH 3/4] zynq: gem: Increase the Rx buffer descriptors to 32 Michal Simek
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Michal Simek @ 2015-05-26 11:40 UTC (permalink / raw)
To: u-boot
From: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Flush and invalidate the rx buffers while sending the
tx packet it self as armv8 does flush also while doing
invalidation.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
drivers/net/zynq_gem.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 22195805e6d6..523f95ccfde4 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -20,6 +20,7 @@
#include <phy.h>
#include <miiphy.h>
#include <watchdog.h>
+#include <asm/system.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
@@ -408,6 +409,11 @@ static int zynq_gem_send(struct eth_device *dev, void *ptr, int len)
addr &= ~(ARCH_DMA_MINALIGN - 1);
size = roundup(len, ARCH_DMA_MINALIGN);
flush_dcache_range(addr, addr + size);
+
+ addr = (u32)priv->rxbuffers;
+ addr &= ~(ARCH_DMA_MINALIGN - 1);
+ size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN);
+ flush_dcache_range(addr, addr + size);
barrier();
/* Start transmit */
@@ -443,8 +449,6 @@ static int zynq_gem_recv(struct eth_device *dev)
if (frame_len) {
u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
addr &= ~(ARCH_DMA_MINALIGN - 1);
- u32 size = roundup(frame_len, ARCH_DMA_MINALIGN);
- invalidate_dcache_range(addr, addr + size);
net_process_received_packet((u8 *)addr, frame_len);
@@ -518,7 +522,7 @@ int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr,
priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
- /* Align bd_space to 1MB */
+ /* Align bd_space to MMU_SECTION_SHIFT */
bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
BD_SPACE, DCACHE_OFF);
--
2.3.5
^ permalink raw reply related [flat|nested] 6+ messages in thread* [U-Boot] [PATCH 3/4] zynq: gem: Increase the Rx buffer descriptors to 32
2015-05-26 11:40 [U-Boot] [PATCH 1/4] zynqmp: gem: Set data bus with to 64bit for arm64 Michal Simek
2015-05-26 11:40 ` [U-Boot] [PATCH 2/4] zynqmp: gem: Flush the rx buffers while transmitting Michal Simek
@ 2015-05-26 11:40 ` Michal Simek
2015-05-26 11:40 ` [U-Boot] [PATCH 4/4] zynq: gem: Setting up WRAP bit for one TX bd Michal Simek
2015-05-27 18:08 ` [U-Boot] [PATCH 1/4] zynqmp: gem: Set data bus with to 64bit for arm64 Joe Hershberger
3 siblings, 0 replies; 6+ messages in thread
From: Michal Simek @ 2015-05-26 11:40 UTC (permalink / raw)
To: u-boot
From: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Increase the Rx Buffer descriptors to 32. This will avoid
Rx buffer descriptors overflow if more packets were received
at one shot before we process the received ones.
This fixes the issue of intermittent timeouts during tftp
on a 1Gb connection with tftp server running on windows.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
drivers/net/zynq_gem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 523f95ccfde4..f0546d75bf71 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -138,7 +138,7 @@ struct emac_bd {
u32 status;
};
-#define RX_BUF 3
+#define RX_BUF 32
/* Page table entries are set to 1MB, or multiples of 1MB
* (not < 1MB). driver uses less bd's so use 1MB bdspace.
*/
--
2.3.5
^ permalink raw reply related [flat|nested] 6+ messages in thread* [U-Boot] [PATCH 4/4] zynq: gem: Setting up WRAP bit for one TX bd
2015-05-26 11:40 [U-Boot] [PATCH 1/4] zynqmp: gem: Set data bus with to 64bit for arm64 Michal Simek
2015-05-26 11:40 ` [U-Boot] [PATCH 2/4] zynqmp: gem: Flush the rx buffers while transmitting Michal Simek
2015-05-26 11:40 ` [U-Boot] [PATCH 3/4] zynq: gem: Increase the Rx buffer descriptors to 32 Michal Simek
@ 2015-05-26 11:40 ` Michal Simek
2015-05-27 18:08 ` [U-Boot] [PATCH 1/4] zynqmp: gem: Set data bus with to 64bit for arm64 Joe Hershberger
3 siblings, 0 replies; 6+ messages in thread
From: Michal Simek @ 2015-05-26 11:40 UTC (permalink / raw)
To: u-boot
Setting up WRAP bit to indicate that this is the last TX BD in the
chain.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
drivers/net/zynq_gem.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index f0546d75bf71..970594a7953c 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -403,7 +403,8 @@ static int zynq_gem_send(struct eth_device *dev, void *ptr, int len)
priv->tx_bd->addr = (u32)ptr;
priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
- ZYNQ_GEM_TXBUF_LAST_MASK;
+ ZYNQ_GEM_TXBUF_LAST_MASK |
+ ZYNQ_GEM_TXBUF_WRAP_MASK;
addr = (u32) ptr;
addr &= ~(ARCH_DMA_MINALIGN - 1);
--
2.3.5
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 1/4] zynqmp: gem: Set data bus with to 64bit for arm64
2015-05-26 11:40 [U-Boot] [PATCH 1/4] zynqmp: gem: Set data bus with to 64bit for arm64 Michal Simek
` (2 preceding siblings ...)
2015-05-26 11:40 ` [U-Boot] [PATCH 4/4] zynq: gem: Setting up WRAP bit for one TX bd Michal Simek
@ 2015-05-27 18:08 ` Joe Hershberger
2015-05-28 7:01 ` Michal Simek
3 siblings, 1 reply; 6+ messages in thread
From: Joe Hershberger @ 2015-05-27 18:08 UTC (permalink / raw)
To: u-boot
Hi Michal,
On Tue, May 26, 2015 at 6:40 AM, Michal Simek <michal.simek@xilinx.com> wrote:
> From: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
>
> Set the data bus width to 64-bit AMBA Databus width in config register.
>
> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> ---
>
> drivers/net/zynq_gem.c | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
> index c723dbb0a694..22195805e6d6 100644
> --- a/drivers/net/zynq_gem.c
> +++ b/drivers/net/zynq_gem.c
> @@ -58,7 +58,14 @@
> #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */
> #define ZYNQ_GEM_NWCFG_MDCCLKDIV2 0x0000c0000 /* Div pclk by 48, 120MHz */
>
> -#define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_NWCFG_FDEN | \
> +#ifdef CONFIG_TARGET_XILINX_ZYNQMP
Isn't there a more explicit define you can use to select this such as
CONFIG_ARM64?
> +# define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */
> +#else
> +# define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */
> +#endif
> +
> +#define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \
> + ZYNQ_GEM_NWCFG_FDEN | \
> ZYNQ_GEM_NWCFG_FSREM | \
> ZYNQ_GEM_NWCFG_MDCCLKDIV)
There is a typo in the subject. with->width.
-Joe
On Tue, May 26, 2015 at 6:40 AM, Michal Simek <michal.simek@xilinx.com> wrote:
> From: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
>
> Set the data bus width to 64-bit AMBA Databus width in config register.
>
> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> ---
>
> drivers/net/zynq_gem.c | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
> index c723dbb0a694..22195805e6d6 100644
> --- a/drivers/net/zynq_gem.c
> +++ b/drivers/net/zynq_gem.c
> @@ -58,7 +58,14 @@
> #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */
> #define ZYNQ_GEM_NWCFG_MDCCLKDIV2 0x0000c0000 /* Div pclk by 48, 120MHz */
>
> -#define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_NWCFG_FDEN | \
> +#ifdef CONFIG_TARGET_XILINX_ZYNQMP
> +# define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */
> +#else
> +# define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */
> +#endif
> +
> +#define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \
> + ZYNQ_GEM_NWCFG_FDEN | \
> ZYNQ_GEM_NWCFG_FSREM | \
> ZYNQ_GEM_NWCFG_MDCCLKDIV)
>
> --
> 2.3.5
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
^ permalink raw reply [flat|nested] 6+ messages in thread* [U-Boot] [PATCH 1/4] zynqmp: gem: Set data bus with to 64bit for arm64
2015-05-27 18:08 ` [U-Boot] [PATCH 1/4] zynqmp: gem: Set data bus with to 64bit for arm64 Joe Hershberger
@ 2015-05-28 7:01 ` Michal Simek
0 siblings, 0 replies; 6+ messages in thread
From: Michal Simek @ 2015-05-28 7:01 UTC (permalink / raw)
To: u-boot
On 05/27/2015 08:08 PM, Joe Hershberger wrote:
> Hi Michal,
>
> On Tue, May 26, 2015 at 6:40 AM, Michal Simek <michal.simek@xilinx.com> wrote:
>> From: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
>>
>> Set the data bus width to 64-bit AMBA Databus width in config register.
>>
>> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
>> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
>> ---
>>
>> drivers/net/zynq_gem.c | 9 ++++++++-
>> 1 file changed, 8 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
>> index c723dbb0a694..22195805e6d6 100644
>> --- a/drivers/net/zynq_gem.c
>> +++ b/drivers/net/zynq_gem.c
>> @@ -58,7 +58,14 @@
>> #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */
>> #define ZYNQ_GEM_NWCFG_MDCCLKDIV2 0x0000c0000 /* Div pclk by 48, 120MHz */
>>
>> -#define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_NWCFG_FDEN | \
>> +#ifdef CONFIG_TARGET_XILINX_ZYNQMP
>
> Isn't there a more explicit define you can use to select this such as
> CONFIG_ARM64?
No problem to use it - fixed in v2.
>
>> +# define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */
>> +#else
>> +# define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */
>> +#endif
>> +
>> +#define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \
>> + ZYNQ_GEM_NWCFG_FDEN | \
>> ZYNQ_GEM_NWCFG_FSREM | \
>> ZYNQ_GEM_NWCFG_MDCCLKDIV)
>
> There is a typo in the subject. with->width.
Fixed too in v2.
Thanks,
Michal
^ permalink raw reply [flat|nested] 6+ messages in thread